SLVSIV1 March   2026 TLV61040-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Peak Current Control
      2. 6.3.2 Soft Start
      3. 6.3.3 Enable
      4. 6.3.4 Undervoltage Lockout
      5. 6.3.5 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Inductor Selection, Maximum Load Current
        2. 7.2.2.2 Setting The Output Voltage
        3. 7.2.2.3 Input and Output Capacitor Selection
        4. 7.2.2.4 Diode Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.2.3 Input and Output Capacitor Selection

The output capacitor is mainly selected to meet the requirements for output ripple and loop stability. This ripple voltage is related to the capacitor capacitance and the equivalent series resistance (ESR). Assuming a ceramic capacitor with zero ESR, use Equation 8 to calculate the minimum capacitance needed for a given ripple.

Equation 8. COUT=ILoadDmaxfswVripple

Where:

  • ILoad = Nominal load current
  • Dmax = Maximum duty cycle in the application
  • fsw = Switching frequency at the nominal load current as calculated previously
  • Vripple = Target peak to peak output voltage ripple

The ESR impact on the output ripple must be considered if tantalum or aluminum electrolytic capacitors are used.

Take care when evaluating the derating of a ceramic capacitor under DC bias, aging, and AC signal. For example, the DC bias can significantly reduce capacitance. A ceramic capacitor can lose more than 50% of the capacitance at the rated voltage. Therefore, always leave margin on the voltage rating to make sure of adequate capacitance at the required output voltage.

TI recommends using the output capacitor with effective capacitance 10µF, which covers the major applications. TI also recommends placing a small 1µF capacitor right across the rectifier diode cathode to the GND pin of the TLV61040-Q1 to reduce the high RMS current loop inductance. The output capacitor affects the small signal control loop stability of the boost regulator. If the output capacitor is below the range, the boost regulator can potentially become unstable. Increasing the output capacitor makes the output voltage ripple smaller in PWM mode.

But if total output capacitance is too large, because the boost converter cannot control inductor current when VIN is close to VOUT, the inductor current increases to a high level during start-up until VOUT is high enough. The larger the COUT and VIN, the higher the peak inrush current. If the peak inductor current is higher than 2.5A, the device has risk to damage. TI recommends total output capacitance for TLV61040-Q1 to be less than 120μF.

Table 7-3 lists the recommended capacitor for the TLV61040-Q1.

Table 7-3 Recommended Output Capacitors for the TLV61040-Q1
PART NUMBERCOUT (µF)RATINGPACKAGEVENDOR(1)
TMK316BLD106KL1025V, X5R1206Taiyo Yuden
CC1206KKX5R8BB1061025V, X5R1206Yageo
CGA5L1X7R1H106K160AC1050V, X7R1206TDK

The ceramic capacitors are an excellent choice for the input decoupling of the step-up converter because the ceramic capacitors have extremely low ESR and are available in small footprints. Input capacitors must be located as close as possible to the device. While a 10µF input capacitor or equivalent is sufficient for the most applications, larger values can be used to reduce input current ripple.

Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or can even damage the device. Additional "bulk" capacitor (electrolytic or tantalum) in this circumstance, must be placed between CIN and the power source lead to reduce ringing that can occur between the inductance of the power source leads and CIN.