SLVSJF7 August   2025 SN74AC09

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4.   4
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Open-Drain CMOS Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

5.6 Switching Characteristics

over operating free-air temperature range; CL = 50pF typical values measured at TA = 25°C (unless otherwise noted). See Parameter Measurement Information
PARAMETER FROM (INPUT) TO (OUTPUT) VCC -40°C to 125°C UNIT
MIN TYP MAX
tPLZ A or B Y 1.5V 15.1 20.9 ns
3.3V ± 0.3V 4.7 6.5 ns
5V ± 0.5V 3.1 4.2 ns
6V 2.6 3.5 ns
tPZL A or B Y 1.5V 16.3 25.9 ns
3.3V ± 0.3V 6.7 9.7 ns
5V ± 0.5V 5 6.8 ns
6V 4.2 5.6 ns
tsk(o) Y 1.5V 0.6 1 ns
6V 0.2 0.4 ns
CPD(1) Any 5V 17 pF
(1) Power dissipation capacitance is calculated using the method described in CMOS Power Consumption and Cpd Calculation.