SLVSJG8A March   2026  – July 2026 TPS25730A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
      1. 6.1.1 TPS25730AD and TPS25730AS - Absolute Maximum Ratings
      2. 6.1.2 TPS25730AD - Absolute Maximum Ratings
      3. 6.1.3 TPS25730AS - Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
      1. 6.3.1 TPS25730AD - Recommended Operating Conditions
      2. 6.3.2 TPS25730AS - Recommended Operating Conditions
    4. 6.4  Recommended Capacitance
    5. 6.5  Thermal Information
      1. 6.5.1 TPS25730AD - Thermal Information
      2. 6.5.2 TPS25730AS Thermal Information
    6. 6.6  Power Supply Characteristics
    7. 6.7  Power Consumption
    8. 6.8  PPHV Power Switch Characteristics - TPS25730AD
    9. 6.9  PP_EXT Characteristics - TPS25730AS
    10. 6.10 Power Path Supervisory
    11. 6.11 CC Cable Detection Parameters
    12. 6.12 CC PHY Parameters
    13. 6.13 Thermal Shutdown Characteristics
    14. 6.14 ADC Characteristics
    15. 6.15 Input/Output (I/O) Characteristics
    16. 6.16 I2C Requirements and Characteristics
    17. 6.17 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD BMC Transmitter
        4. 8.3.1.4 USB-PD BMC Receiver
        5. 8.3.1.5 Squelch Receiver
      2. 8.3.2  Power Management
        1. 8.3.2.1 Power-On And Supervisory Functions
        2. 8.3.2.2 VBUS LDO
      3. 8.3.3  Power Paths
        1. 8.3.3.1 TPS25730AD Internal Powerpath
        2. 8.3.3.2 External Powerpath Control PP_EXT
      4. 8.3.4  Cable Plug and Orientation Detection
      5. 8.3.5  Overvoltage Protection (CC1, CC2)
      6. 8.3.6  Default Behavior Configuration (ADCINx)
      7. 8.3.7  ADC
      8. 8.3.8  Digital Interfaces
        1. 8.3.8.1 GPIO
        2. 8.3.8.2 I2C Interface
          1. 8.3.8.2.1 I2C Interface Description
            1. 8.3.8.2.1.1 I2C Clock Stretching
            2. 8.3.8.2.1.2 Unique Address Interface
            3. 8.3.8.2.1.3 Pin Strapping to Configure Default Behavior
      9. 8.3.9  Digital Core
      10. 8.3.10 Minimum Voltage Configuration
      11. 8.3.11 Maximum Voltage Configuration
      12. 8.3.12 Sink Current Configuration
      13. 8.3.13 Auto-negotiate Sink Minimum Power
      14. 8.3.14 Extended Sink Capabilities Power Delivery Power
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power States
      2. 8.4.2 Schottky for Current Surge Protection
      3. 8.4.3 Thermal Shutdown
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 3.3V Power
        1. 9.3.1.1 VIN_3V3 Input Switch
      2. 9.3.2 1.5V Power
      3. 9.3.3 Recommended Supply Load Capacitance
    4. 9.4 Layout
      1. 9.4.1 TPS25730AD - Layout
        1. 9.4.1.1 Layout Guidelines
          1. 9.4.1.1.1 Top Placement and Bottom Component Placement and Layout
        2. 9.4.1.2 Layout Example
        3. 9.4.1.3 Component Placement
        4. 9.4.1.4 Routing VBUS, VIN_3V3, LDO_3V3, LDO_1V5
        5. 9.4.1.5 Routing CC and GPIO
      2. 9.4.2 TPS25730AS - Layout
        1. 9.4.2.1 Layout Guidelines
          1. 9.4.2.1.1 Top Placement and Bottom Component Placement and Layout
        2. 9.4.2.2 Layout Example
        3. 9.4.2.3 Component Placement
        4. 9.4.2.4 Routing VBUS, PPHV, VIN_3V3, LDO_3V3, LDO_1V5
        5. 9.4.2.5 Routing CC and GPIO
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
8.3.8.2.1.1 I2C Clock Stretching

The TPS25730A features clock stretching for the I2C protocol. The TPS25730A target I2C port can hold the clock line (SCL) low after receiving (or sending) a byte, indicating that the bus is not yet ready to process more data. The controller communicating with the target must not finish the transmission of the current bit and must wait until the clock line actually goes high. When the target is clock stretching, the clock line remains low.

The controller must wait until the clock line transitions high plus an additional minimum time (4μs for standard 100kbps I2C) before pulling the clock low again.

Any clock pulse can be stretched and typically the clock pulse before or after the acknowledgment bit is stretched.