SLVSJM6 November 2025 MSPM0G5187
UNICOMMI2CT Module
Functional
CPU reads RXFIFO failure when I2C clock much lower than CPU clock
In UNICOMMI2CT RX mode, the RXDONE interrupt flag asserts immediately after the last bit of the received frame. However, the RXFIFO buffer content updates exhibit a 2-clock-cycle latency relative to RXDONE assertion. If the CPU initiates an RXFIFO read operation more than 2 UNICOMMI2CT clock cycles after RXDONE flag triggering, it may access stale FIFO data, leading to a data integrity violation. This will be a problem especially when UNICOMMI2CT clock is much lower than CPU clock.
Add a fix delay before reading the RXFIFO.