SLVSJW3 September   2025 SN74ACT165

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4.   4
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     14
    8. 5.7 Switching Characteristics
    9. 5.8 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 TTL-Compatible CMOS Inputs
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

7.4 Device Functional Modes

Table 7-1 and Table 7-2 list the functional modes of the SN74ACT165.

Table 7-1 Operating Mode Table
INPUTS(1) FUNCTION
SH/LD CLK CLK INH
L X X Parallel load(2)
H H X No change
H X H No change
H L ↑ Shift(3)
H ↑ L Shift(3)
(1) H = High Voltage Level, L = Low Voltage Level, X = Don't Care, ↑ = Low to High transition
(2) Parallel load : Values at inputs A through H are loaded to respective internal registers.
(3) Shift : Content of each internal register shifts towards serial output QH. Data at SER is shifted into the first register.
Table 7-2 Output Function Table
INTERNAL REGISTERS(1)(2) OUTPUTS(3)
A — G H Q Q
X L L H
X H H L
(1) Internal registers refer to the shift registers inside the device. These values are set by either loading data from the parallel inputs, or by clocking data in from the serial input.
(2) H = High voltage level, L = Low voltage level, X = Don't care
(3) H = Driving high, L = Driving low