SLVSJX5 September   2025 SN74ACT3G97

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4.   4
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 TTL-Compatible Schmitt-Trigger CMOS Inputs
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
    5. 7.5 Combinatorial Logic Configurations
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 Power Supply Recommendations
      5. 8.2.5 Layout
        1. 8.2.5.1 Layout Guidelines
        2. 8.2.5.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

8.2.5.1 Layout Guidelines

  • Bypass capacitor placement
    • Place near the positive supply terminal of the device
    • Provide an electrically short ground return path
    • Use wide traces to minimize impedance
    • Keep the device, capacitors, and traces on the same side of the board whenever possible
  • Signal trace geometry
    • 8mil to 12mil trace width
    • Lengths less than 12cm to minimize transmission line effects
    • Avoid 90° corners for signal traces
    • Use an unbroken ground plane below signal traces
    • Flood fill areas around signal traces with ground
    • Parallel traces must be separated by at least 3x dielectric thickness
    • For traces longer than 12cm
      • Use impedance controlled traces
      • Source-terminate using a series damping resistor near the output
      • Avoid branches; buffer each signal that must branch separately