SLVSJZ8 September   2025 SN74LV8T574

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4.   4
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Noise Characteristics
    9. 5.9 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 Balanced CMOS 3-State Outputs
      2. 7.2.2 Latching Logic with Known Power-Up State
      3. 7.2.3 LVxT Enhanced Input Voltage
        1. 7.2.3.1 Up Translation
        2. 7.2.3.2 Down Translation
      4. 7.2.4 Clamp Diode Structure
    3. 7.3 Functional Block Diagram
    4. 7.4 Device Functional Modes
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

5.6 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC TA = 25°C -40°C to 85°C -40°C to 125°C UNIT
MIN MAX MIN MAX MIN MAX
tW Pulse duration CLK 1.8V 3.7 3.7 3.7 ns
tSU Setup time Data before CLK rising edge 1.8V 1.9 2.1 2.2 ns
tH Hold time Data after CLK rising edge 1.8V 1 1.1 1.1 ns
tW Pulse duration CLK 2.5V 3.7 3.7 3.7 ns
tSU Setup time Data before CLK rising edge 2.5V 1.5 1.7 1.8 ns
tH Hold time Data after CLK rising edge 2.5V 0.6 0.7 0.7 ns
tW Pulse duration CLK 3.3V 3.7 3.7 3.7 ns
tSU Setup time Data before CLK rising edge 3.3V 1.3 1.6 1.6 ns
tH Hold time Data after CLK rising edge 3.3V 0.5 0.5 0.5 ns
tW Pulse duration CLK 5V 3.7 3.7 3.7 ns
tSU Setup time Data before CLK rising edge 5V 0.2 0.6 0.6 ns
tH Hold time Data after CLK rising edge 5V 0.4 0.4 0.4 ns