The TDEL3G510 device contains three digitally timed falling-edge delay circuits.

When the input transitions from high to low, the internal timer starts. When the timer reaches the predefined delay value, the output transitions from high to low and the timer is disabled. When the input transitions from low to high, the timer is reset and disabled, awaiting the next falling-edge delay operation.

The falling-edge delay feature provides inherent filtering behavior for active-low signals, maintaining the output in the high state as long as the input does not remain low longer than the predefined delay time.

The internal oscillator turns off when not in use. When a delay is being measured, the oscillator is turned on and is shared by all channels.

During the power-up ramp, the outputs remain in a high-impedance state until the internal power-on reset circuit enables normal device operation.