SLVSKD0 March   2026 TDEL3G510

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4.   4
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Naming Convention
      2. 7.3.2 Timing Mechanism and Accuracy
      3. 7.3.3 CMOS Push-Pull Outputs
      4. 7.3.4 CMOS Schmitt-Trigger Inputs
      5. 7.3.5 Latching Logic with Known Power-Up State
      6. 7.3.6 Clamp Diode Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Startup Operation
      2. 7.4.2 On-State Operation
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

8.2 Typical Application

In this application, one channel of the TDEL3G510 is used to delay falling edges on an input signal. The circuit configuration is shown in Figure 8-1.

TDEL3G510 Falling Edge Delay Schematic Using the TDEL3G510 Figure 8-1 Falling Edge Delay Schematic Using the TDEL3G510