SLVSKD7 April   2026 TDEL1G533

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4.   4
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     14
    8. 5.7 Switching Characteristics
    9. 5.8 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3.     21
    4. 7.3 Feature Description
      1. 7.3.1 Naming Convention
      2. 7.3.2 Timing Mechanism and Accuracy
      3. 7.3.3 CMOS Push-Pull Outputs
      4. 7.3.4 Open-Drain CMOS Outputs
      5. 7.3.5 CMOS Schmitt-Trigger Inputs
      6. 7.3.6 Latching Logic with Known Power-Up State
      7. 7.3.7 Clamp Diode Structure
    5.     30
    6. 7.4 Device Functional Modes
      1. 7.4.1 Startup Operation
      2. 7.4.2 On-State Operation
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

7.4.2 On-State Operation

The table below lists the on-state functional modes for the TDEL1G533.

Table 7-1 Function Table
INPUTS(1) OUTPUTS(2)
RST T T Q' Q Q PT
H X X X L H L
L L H L L H L(3)
L L H H H L L(3)
L H L L L H L(3)
L H L H H L L(3)
L H H L H L Z
L L L L H L Z
L H H H L(4) H(4) Z
L L L H L(4) H(4) Z
(1) H = high voltage level, L = low voltage level, Q' = previous Q state
(2) L = driving low, H = driving high, Z = high impedance
(3) The PT output remains in the high-impedance state after the input is released for the pre-configured debounce delay time.
(4) The Q and Q outputs change to the shown state after the input is held in the described condition for the pre-configured shut-off delay time.