SLVSKD7 April   2026 TDEL1G533

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4.   4
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     14
    8. 5.7 Switching Characteristics
    9. 5.8 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3.     21
    4. 7.3 Feature Description
      1. 7.3.1 Naming Convention
      2. 7.3.2 Timing Mechanism and Accuracy
      3. 7.3.3 CMOS Push-Pull Outputs
      4. 7.3.4 Open-Drain CMOS Outputs
      5. 7.3.5 CMOS Schmitt-Trigger Inputs
      6. 7.3.6 Latching Logic with Known Power-Up State
      7. 7.3.7 Clamp Diode Structure
    5.     30
    6. 7.4 Device Functional Modes
      1. 7.4.1 Startup Operation
      2. 7.4.2 On-State Operation
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

7.1 Overview

The TDEL1G533 device is a single momentary switch interface with latching output and debounced pass-through functionality.

The device has two input options: T for active-low switches and T for active-high switches. The T input includes an internal 1MΩ pull-up resistor, allowing the input to be left disconnected when unused and eliminating the need for an external pull-up resistor. The T input includes an internal 1MΩ pull-down resistor, providing similar convenience for active-high switch applications without requiring additional external components.

When either input is activated (a high signal at T or a low signal at T), the output latches to the active state with Q high and Q low. This output state is maintained indefinitely as long as power is applied to the device.

The device includes an active-high reset input (RST) with an internal 1MΩ pull-down resistor for when the pin is unused. When RST is activated, the output immediately resets with Q returning to low and Q returning to high.

The pass-through output (PT) is an open-drain output that copies the input signal after debouncing. The positive (T) input is reproduced at the PT output with a short delay on the falling edge due to the debounce mechanism. The negative (T) input is inverted at the PT output, also producing a positive waveform with a short delay on the falling edge due to the debounce mechanism. In short, either input will produce a positive output pulse. The RST signal overrides the T or T inputs, forcing the output low as long as RST is active.

During the power-up ramp, the outputs remain in a high-impedance state until the internal power-on reset circuit enables normal device operation.