SLVSKO1 November   2025 SN74AHC3G99-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4.   4
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Noise Characteristics
    8. 5.8 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Combinatorial Logic Configurations
    4. 7.4 Feature Description
      1. 7.4.1 Balanced CMOS 3-State Outputs
      2. 7.4.2 CMOS Schmitt-Trigger Inputs
      3. 7.4.3 Wettable Flanks
      4. 7.4.4 Clamp Diode Structure
    5. 7.5 Device Functional Modes
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

3 Description

The SN74AHC3G99-Q1 device contains three independent configurable logic gates with 3-state outputs. Each gate has four inputs and performs the Boolean function Y = (A • C + B • C) ⊕ D. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The user can choose logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer by connecting the inputs A, B, C, and D appropriately.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
SN74AHC3G99-Q1 PW (TSSOP, 20) 6.5mm × 6.4mm 6.5mm × 4.4mm
DGS (VSSOP, 20) 5.1mm × 4.9mm 5.1mm × 3.0mm
RKS (VQFN, 20) 4.5mm × 2.5mm 4.5mm × 2.5mm
(1) For more information, see Mechanical, Packaging, and Orderable Information.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
SN74AHC3G99-Q1 Functional Block Diagram Functional Block Diagram