SLVSLA2A February   2026  – July 2026 TPUL1G313-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     13
    8. 5.7 Switching Characteristics
    9. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 State Machine Description
        1. 7.1.1.1 Ready
        2. 7.1.1.2 RC Measurement Cycle
          1. 7.1.1.2.1 Discharge
          2. 7.1.1.2.2 Monitor
          3. 7.1.1.2.3 Timer Count Decision
          4. 7.1.1.2.4 Cycle Count Decision
          5. 7.1.1.2.5 Increment Cycle Counter
          6. 7.1.1.2.6 Reset Timer Counter
          7. 7.1.1.2.7 Save Timer Count
        3. 7.1.1.3 Digital Timer Cycle
          1. 7.1.1.3.1 Reset Timer Counter
          2. 7.1.1.3.2 Delay
          3. 7.1.1.3.3 Increment Cycle Counter
          4. 7.1.1.3.4 Cycle Count Decision
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Naming Convention
      2. 7.3.2 Retriggerable One-Shot
      3. 7.3.3 Extended RC Timed One-Shot
      4. 7.3.4 Balanced CMOS Push-Pull Outputs
      5. 7.3.5 CMOS Schmitt-Trigger Inputs
      6. 7.3.6 Latching Logic with Known Power-Up State
      7. 7.3.7 Partial Power Down (Ioff)
      8. 7.3.8 Clamp Diode Structure
      9. 7.3.9 Over-Voltage Tolerant Inputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off-State Operation
      2. 7.4.2 Startup Operation
      3. 7.4.3 On-State Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 1s Pulse Generator
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Timing Components
          2. 8.2.1.1.2 Input Considerations
          3. 8.2.1.1.3 Output Considerations
          4. 8.2.1.1.4 Power Considerations
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
7.1.1.2.1 Discharge
  • Behavior
    • Timer counter runs from currently selected clock source
    • RC = Low
    • Q = High
  • Transitions
    • In
      • From any state, trigger input
    • Out
      • To ready state, clear active
      • To monitor state, VRC ≤ Vrefl