SLVSLL3 June   2026 TMUXHS4446-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 High-Speed Performance Parameters
    7. 5.7 Switching Characteristics
    8. 5.8 I2C Timing Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High-Speed Differential Signal Switching
      2. 6.3.2 Low-Speed SBU Signal Switching
      3. 6.3.3 GPIO and I2C Control Modes
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.4 Device Functional Modes

This section describes how to configure the TMUXHS4446-Q1 control pins to configure device modes and mux configurations.

Table 6-1 shows how MODE0 and MODE1 pins are used to set device control configuration modes.

Table 6-1 Control Mode Configuration
Control ModeMODE0MODE1
GPIO/Pin Control Mode0X
I2C (1.8V logic)10
I2C (3.3V logic)11

Table 6-2 shows I2C Register sets. A1 and A0 (Byte 1, bits 2 and 1) are set by pins 35 and 14. CONF[2-0] (Byte 3, bits 2-0) sets the device configurations in I2C mode.

Table 6-2 I2C Control
Byte # & DescriptionRegister Bits
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
Byte 1, I2C Secondary Target address10101A1A00/1 (W/R)
Byte 2, Device ID (read only)00000000
Byte 3, Selection control (read/write)00000CONF[2]CONF[1]CONF[0]

Table 6-3 shows how CONF[2:0] pins in GPIO mode and registers Byte 3, bits 2-0 (CONF[2-0]) as shown in Table 6-2 sets mux configurations in source applications.

Table 6-3 High-Speed and Low-Speed Channel Mapping for Source Applications
System-Side ChannelConnector-Side Channel Connected To System-Side Channel
Open (powered down)Open (powered on)USB-C USB 3.xDP Alt Mode Receptacle DFP Pin Assignment (Source)
USB SS onlyUSB SS only FlipC, E4 Ln DPC, E Flip4 Ln DPD2 Ln DP + USB SSD Flip2 Ln DP + USB SS
CONF[2:0] = 000CONF[2:0] = 001CONF[2:0] = 100CONF[2:0] = 101CONF[2:0] = 010CONF[2:0] = 011CONF[2:0] = 110CONF[2:0] = 111
SSTXXXCTX1CTX2XXCTX1CTX2
SSRXXXCRX1CRX2XXCRX1CRX2
DP0XXXXCRX2CRX1CRX2CRX1
DP1XXXXCTX2CTX1CTX2CTX1
DP2XXXXCTX1CTX2XX
DP3XXXXCRX1CRX2XX
AUX+XXXXSBU1SBU2SBU1SBU2
AUX-XXXXSBU2SBU1SBU2SBU1

Figure 6-1 shows a pictorial view of the TMUXHS4446-Q1 mux configurations for a source application based on Table 6-3. In this illustration all signals are differential with both positive and negative pins, but shown as single for brevity.

TMUXHS4446-Q1 TMUXHS4446-Q1 Signal Flow Diagrams in Different Configurations for Source ApplicationsFigure 6-1 TMUXHS4446-Q1 Signal Flow Diagrams in Different Configurations for Source Applications

The sink side signal flow can also be constructed based on Table 6-4.

Table 6-4 High-Speed and Low-Speed Channel Mapping for Sink Applications
System-Side ChannelConnector-Side Channel Connected To System-Side Channel
Open (powered down)Open (powered on)USB-C USB 3.xDP Alt Mode Receptacle UFP Pin Assignment (Sink)
USB SS onlyUSB SS only FlipC4 Ln DPC Flip4 Ln DPD2 Ln DP + USB SSD Flip2 Ln DP + USB SS
CONF[2:0] = 000CONF[2:0] = 001CONF[2:0] = 100CONF[2:0] = 101CONF[2:0] = 010CONF[2:0] = 011CONF[2:0] = 110CONF[2:0] = 111
SSTXXXCTX1CTX2XXCTX1CTX2
SSRXXXCRX1CRX2XXCRX1CRX2
DP0XXXXCTX2CTX1CTX2CTX1
DP1XXXXCRX2CRX1CRX2CRX1
DP2XXXXCRX1CRX2XX
DP3XXXXCTX1CTX2XX
AUX+XXXXSBU2SBU1SBU2SBU1
AUX-XXXXSBU1SBU2SBU1SBU2