SLVSLL3 June   2026 TMUXHS4446-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 High-Speed Performance Parameters
    7. 5.7 Switching Characteristics
    8. 5.8 I2C Timing Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High-Speed Differential Signal Switching
      2. 6.3.2 Low-Speed SBU Signal Switching
      3. 6.3.3 GPIO and I2C Control Modes
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.3 Application Curves

Figure 7-2 through Figure 7-3 illustrate DisplayPort 1.4 Tx compliance results at HBR3 8.1Gbps. Eye diagrams (in scope, no cable model) are compared from the baseline setup and from the same setup plus TMUXHS4446-Q1 board. The diagrams are for lane 0. Other lanes also result in to similar eye diagrams. Jitter degradation through TMUXHS4446-Q1 is minimal.

TMUXHS4446-Q1 8.1Gbps DP Compliance Eye Diagram - Baseline Setup (no DUT)Figure 7-2 8.1Gbps DP Compliance Eye Diagram - Baseline Setup (no DUT)
TMUXHS4446-Q1 8.1Gbps DP Compliance Eye Diagram - with TMUXHS4446-Q1Figure 7-3 8.1Gbps DP Compliance Eye Diagram - with TMUXHS4446-Q1

Figure 7-4 through Figure 7-5 illustrate USB 3.x Gen2 Tx compliance results at 10Gbps. Eye diagrams (in scope, near end) are compared from the baseline setup and from the same setup plus TMUXHS4446-Q1 board. The diagrams are for lane 0. Other lanes also result in to similar eye diagrams. Jitter degradation through TMUXHS4446-Q1 is minimal.

TMUXHS4446-Q1 10Gbps USB Compliance Eye Diagram - Baseline Setup (no DUT)Figure 7-4 10Gbps USB Compliance Eye Diagram - Baseline Setup (no DUT)
TMUXHS4446-Q1 10Gbps USB Compliance Eye Diagram - with TMUXHS4446-Q1Figure 7-5 10Gbps USB Compliance Eye Diagram - with TMUXHS4446-Q1