SLVSLR1 August   2026 CD74HC4094-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     13
    8. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 Balanced CMOS Push-Pull Outputs
      2. 7.2.2 Balanced CMOS 3-State Outputs
      3. 7.2.3 Latching Logic
      4. 7.2.4 Standard CMOS Inputs
      5. 7.2.5 Clamp Diode Structure
      6. 7.2.6 Positive Clamp Diodes
    3. 7.3 Functional Block Diagram
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
        4. 8.2.1.4 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.2.6 Positive Clamp Diodes

The CD74HC4094-Q1 includes inputs with positive clamp diodes. The positive clamp diodes prevent the input voltage from reaching levels dangerous to the device, holding the input voltage (VA) to approximately VCC + 0.5V as long as the input clamp current (IIK) does not exceed the maximum limit provided in Absolute Maximum Ratings.

The input can draw significant current when the input voltage (VA) exceeds the supply voltage (VS) because the diode is forward biased and must be externally limited to avoid damage to the device. Additionally, the input clamp current, IIK, can be several orders of magnitude larger than ICC, resulting in current returning to the supply (the reverse of normal operation) which must be accounted for by the system designer, as shown in Figure 7-2.

A resistor (R) can be used to prevent excessive current on the input as shown in Figure 7-2. The resistor value can be determined with R ≥ (VIN - VA)/IIK(max), with VA ⋍ VS + 0.5V. The system-level input voltage (VIN) may exceed the supply voltage (VS) because the device input voltage (VA) is held at approximately VS + 0.5V by the clamp diode.

CD74HC4094-Q1 Example with resistor to limit input current Figure 7-2 Example with resistor to limit input current