SLVSLX8 August   2026 SN74UVP1G16

ADVANCE INFORMATION  

  1.   1
  2.   2
  3. 1 Features
  4. 2 Applications
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Overview
  10. 8 Functional Block Diagram
  11. 9 Detailed Description
    1. 9.1 Feature Description
      1. 9.1.1 Open-Drain CMOS Outputs
      2. 9.1.2 CMOS Schmitt-Trigger Inputs
  12. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Power Considerations
        2. 10.2.1.2 Input Considerations
        3. 10.2.1.3 Output Considerations
      2. 10.2.2 Detailed Design Procedure
    3. 10.3 Application Curves
    4. 10.4 Power Supply Recommendations
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  14. 12Revision History
  15. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information
    2. 13.2 Mechanical Data

Description

The SN74UVP1G16 device is an Inverter Buffer with a Schmitt-Trigger input and an Open-Drain output.

Package Information
PART NUMBER PACKAGE (1) PACKAGE SIZE (2)
SN74UVP1G16 DBV (SOT-23, 5) 2.90mm × 1.60mm
SN74UVP1G16 DCK (SC-70, 5) 2.00mm × 1.25mm
DRY (USON, 6) 1.45mm × 1.00mm
DSF (X2SON, 6) 1.00mm × 1.00mm
DPW (X2SON, 5) 0.80mm × 0.80mm
For more information, see Section 13.
The body size (length × width) is a nominal value and does not include pins.
SN74UVP1G16 Logic Diagram Logic Diagram