SLVSLY2 August   2026 SN74UVP1G37-Q1

ADVANCE INFORMATION  

  1.   1
  2.   2
  3. 1 Features
  4. 2 Applications
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Open-Drain CMOS Outputs
      2. 7.3.2 CMOS Schmitt-Trigger Inputs
    4. 7.4 Device Functional Modes
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily for the examples listed in the following table. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt < 3ns.

The outputs are measured individually with one input transition per measurement.

TEST RL CL ΔV VCC
tpd 20KΩ 5pF 0.07V 0.7V
0.08V 0.8V
10pF 0.1V 1.0V
5KΩ 10pF 0.12V 1.2V
15pF 0.15V 1.5V
0.18V 1.8V
30pF 0.2V 2.5V
0.3V 3.3V
SN74UVP1G37-Q1 Load Circuit for Open-Drain Outputs
(1) CL includes probe and test-fixture capacitance.
(2) RL = 5kΩ or 20kΩ for enable and disable time measurement. RL = 1MΩ for measuring propagation delays, setup and hold times, and pulse width.
Figure 6-1 Load Circuit for Open-Drain Outputs
SN74UVP1G37-Q1 Voltage Waveforms Propagation Delays
(1) If RL = 5kΩ, the time between tPLZ and tPZL is the same as disable and enable time.
(2) If RL = 1MΩ, tPLZ and tPZL are the same as tpd.
Figure 6-2 Voltage Waveforms Propagation Delays