SLVSLY5 June   2026 SN74UVP1G07-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

3 Description

The SN74UVP1G07-Q1 device is a single-buffer gate with open-drain output.

Package Information
PART NUMBER PACKAGE (1) PACKAGE SIZE(2)
SN74UVP1G07-Q1 DBV (SOT-23, 5) 2.90mm × 1.60mm
DCK (SC-70, 5) 2.00mm × 1.25mm
DTX (X2SON, 5) 1.10mm × 0.85mm
DRY (USON, 6) 1.45mm × 1.00mm
DSF (X2SON, 6) 1.00mm × 1.00mm
DPW (X2SON, 5) 0.80mm × 0.80mm
(1) For more information, see Section 11.
(2) The body size (length × width) is a nominal value and does not include pins.
SN74UVP1G07-Q1 Simplified Schematic Simplified Schematic