SLVSML2 August   2026 AFE7900-SEP

PRODMIX  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Transmitter Electrical Characteristics
    6. 4.6  RF ADC Electrical Characteristics
    7. 4.7  PLL/VCO/Clock Electrical Characteristics
    8. 4.8  Digital Electrical Characteristics
    9. 4.9  Power Supply Electrical Characteristics
    10. 4.10 Timing Requirements
    11. 4.11 Switching Characteristics
    12. 4.12 Typical Characteristics
      1. 4.12.1  RX Typical Characteristics 30MHz and 400MHz
      2. 4.12.2  RX Typical Characteristics at 800MHz
      3. 4.12.3  RX Typical Characteristics 1.75GHz to 1.9GHz
      4. 4.12.4  RX Typical Characteristics 2.6GHz
      5. 4.12.5  RX Typical Characteristics 3.5GHz
      6. 4.12.6  RX Typical Characteristics 4.9GHz
      7. 4.12.7  RX Typical Characteristics 6.8GHz
      8. 4.12.8  TX Typical Characteristics at 30MHz and 400MHz
      9. 4.12.9  TX Typical Characteristics at 800MHz
      10. 4.12.10 TX Typical Characteristics at 1.8GHz
      11. 4.12.11 TX Typical Characteristics at 2.6GHz
      12. 4.12.12 TX Typical Characteristics at 3.5GHz
      13. 4.12.13 TX Typical Characteristics at 4.9GHz
      14. 4.12.14 TX Typical Characteristics at 7.1GHz
      15. 4.12.15 PLL and Clock Typical Characteristics
  6. 5Device and Documentation Support
    1. 5.1 Receiving Notification of Documentation Updates
    2. 5.2 Support Resources
    3. 5.3 Trademarks
    4. 5.4 Electrostatic Discharge Caution
    5. 5.5 Glossary
  7. 6Revision History
  8. 7Mechanical, Packaging, and Orderable Information

4.10 Timing Requirements

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS, fDAC = 8847.36MSPS; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
MINNOMMAXUNIT
Timing: SYSREF+/-
ts(SYSREF)Setup Time, SYSREF+/- Valid to Rising Edge of CLK+/-50ps
th(SYSREF)Hold Time, SYSREF+/- Valid after Rising Edge of CLK+/-50ps
Timing: Serial ports
ts(SENB)Setup Time, SENB to Rising Edge of SCLK15ns
th(SENB)Hold Time, SENB after last Rising Edge of SCLK (1)5 + tSCLKns
ts(SDIO)Setup Time, SDIO valid to Rising Edge of SCLK15ns
th(SDIO)Hold Time, SDIO valid after Rising Edge of SCLK5ns
t(SCLK)_WMinimum SCLK period: registers write25ns
t(SCLK)_RMinimum SCLK period: registers read50ns
td(data_out)Minimum Data Output delay after Falling Edge of SCLK0ns
Maximum Data Output delay after Falling Edge of SCLK15ns
tRESETMinimum RESETZ Pulse Width1ms
(1) SDEN\\ need to be held one more extra clock cycle with the last SCLK edge