SLVSML2 August   2026 AFE7900-SEP

PRODMIX  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Transmitter Electrical Characteristics
    6. 4.6  RF ADC Electrical Characteristics
    7. 4.7  PLL/VCO/Clock Electrical Characteristics
    8. 4.8  Digital Electrical Characteristics
    9. 4.9  Power Supply Electrical Characteristics
    10. 4.10 Timing Requirements
    11. 4.11 Switching Characteristics
    12. 4.12 Typical Characteristics
      1. 4.12.1  RX Typical Characteristics 30MHz and 400MHz
      2. 4.12.2  RX Typical Characteristics at 800MHz
      3. 4.12.3  RX Typical Characteristics 1.75GHz to 1.9GHz
      4. 4.12.4  RX Typical Characteristics 2.6GHz
      5. 4.12.5  RX Typical Characteristics 3.5GHz
      6. 4.12.6  RX Typical Characteristics 4.9GHz
      7. 4.12.7  RX Typical Characteristics 6.8GHz
      8. 4.12.8  TX Typical Characteristics at 30MHz and 400MHz
      9. 4.12.9  TX Typical Characteristics at 800MHz
      10. 4.12.10 TX Typical Characteristics at 1.8GHz
      11. 4.12.11 TX Typical Characteristics at 2.6GHz
      12. 4.12.12 TX Typical Characteristics at 3.5GHz
      13. 4.12.13 TX Typical Characteristics at 4.9GHz
      14. 4.12.14 TX Typical Characteristics at 7.1GHz
      15. 4.12.15 PLL and Clock Typical Characteristics
  6. 5Device and Documentation Support
    1. 5.1 Receiving Notification of Documentation Updates
    2. 5.2 Support Resources
    3. 5.3 Trademarks
    4. 5.4 Electrostatic Discharge Caution
    5. 5.5 Glossary
  7. 6Revision History
  8. 7Mechanical, Packaging, and Orderable Information

4.7 PLL/VCO/Clock Electrical Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; Reference clock input frequency 491.52MHz (unless otherwise noted), fDAC = fVCO, fOUT = fDAC/4, normalized to fVCO.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
fVCO1VCO1 min frequency7.2GHz
VCO1 max frequency7.68GHz
fVCO2VCO2 min frequency8.848GHz
VCO2 max frequency9.216GHz
fVCO3VCO3 min frequency9.8304GHz
VCO3 max frequency10.24GHz
fVCO4VCO4 min frequency11.7965GHz
VCO4 max frequency12.288GHz
DIVDACDAC sample rate divider1, 2 or 3
DIVFBADCADC sample rate divider from DAC sample rate1, 2, 3, 4, 6 or 8
DIVRXADCADC sample rate divider1, 2, 3, 4, 6 or 8
PNVCOClosed Loop Phase Noise FPLL = 11.79848 GHz FREF=491.52MHz600kHz-113dBc/Hz
800kHz-116dBc/Hz
1MHz-119dBc/Hz
1.8MHz-125dBc/Hz
5MHz-133dBc/Hz
50MHz–141dBc/Hz
Closed Loop Phase Noise FPLL=8.84736 GHz FREF=491.52MHz600kHz-114dBc/Hz
800kHz–118dBc/Hz
1MHz–120dBc/Hz
1.8MHz–127dBc/Hz
5MHz–135dBc/Hz
50MHz–142dBc/Hz
Closed Loop Phase Noise FPLL= 9.8403 GHz FREF=491.52MHz600kHz–113dBc/Hz
800kHz–116dBc/Hz
1MHz–119dBc/Hz
1.8MHz–125dBc/Hz
5MHz–134dBc/Hz
50MHz–140dBc/Hz
Closed Loop Phase Noise FPLL= 7.86432GHz FREF=491.52MHz600kHz–116dBc/Hz
800kHz–119dBc/Hz
1MHz–122dBc/Hz
1.8MHz–127dBc/Hz
5MHz–136dBc/Hz
50MHz–143dBc/Hz
FrmsClock PLL integrated phase error(1)fPLL=11.79848 GHz, [1KHz, 100MHz]-43.4dBc/Hz
fPLL=8.8536 GHz, [1KHz, 100MHz]-47.6dBc/Hz
fPLL=9.8304 GHz, [1KHz, 100MHz]-46.2dBc/Hz
fPFDPFD frequency100500MHz
PNpll_flatNormalized PLL flat NoisefVCO = 11796.48MHz–226.5dBc/Hz
FREFInput Clock frequency0.112GHz
VSSInput Clock level0.61.8Vppdiff
CouplingAC Coupling Only
REFCLK input impedance(2)Parallel resistance100Ω
Parallel capacitance0.5pF
(1) Single Sideband, not including the reference clock contribution
(2) Refer to S11 data available from TI for impedance vs frequency