SLVSN07 September   2026 SN74LVC1G98B-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5.   5
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 CMOS Schmitt-Trigger Inputs
      3. 7.3.3 Partial Power Down (Ioff)
      4. 7.3.4 Clamp Diode Structure
      5. 7.3.5 Over-Voltage Tolerant Inputs
    4. 7.4 Device Functional Modes
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

7.4 Device Functional Modes

Table 7-1 lists the functional modes of the SN74LVC1G98B-Q1 and Table 7-2 lists the logic configuration images.

Table 7-1 Function Table
INPUTS(1) OUTPUT(2)
C B A Y
L L L H
L L H H
L H L L
L H H L
H L L H
H L H L
H H L H
H H H L
(1) H = High Voltage Level, L = Low Voltage Level
(2) H = Driving High, L = Driving Low
Table 7-2 Logic Configurations
LOGIC FUNCTION FIGURE NO.
2-to-1 data selector with inverted output Figure 7-2
2-input NAND gate Figure 7-3
2-input NOR gate with one inverted input Figure 7-4
2-input NAND gate with one inverted input Figure 7-5
2-input NOR gate Figure 7-6
Non-inverted buffer Figure 7-7
Inverter Figure 7-8
SN74LVC1G98B-Q1 2-to-1 Data Selector With Inverted OutputFigure 7-2 2-to-1 Data Selector With Inverted Output
SN74LVC1G98B-Q1 2-Input NOR Gate With One Inverted InputFigure 7-4 2-Input NOR Gate With One Inverted Input
SN74LVC1G98B-Q1 2-Input NOR GateFigure 7-6 2-Input NOR Gate
SN74LVC1G98B-Q1 2-Input NAND GateFigure 7-3 2-Input NAND Gate
SN74LVC1G98B-Q1 2-Input NAND Gate With One Inverted InputFigure 7-5 2-Input NAND Gate With One Inverted Input
SN74LVC1G98B-Q1 Non-Inverted BufferFigure 7-7 Non-Inverted Buffer
SN74LVC1G98B-Q1 Inverter Figure 7-8 Inverter