SLVU097B October   2003  – October 2021 TPS54350

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification Summary
    3. 1.3 Modifications
      1. 1.3.1 Output Voltage Setpoint
      2. 1.3.2 Switching Frequency
      3. 1.3.3 Input Filter
      4. 1.3.4 UVLO Programming
      5. 1.3.5 Synchronization
      6. 1.3.6 Power Good
      7. 1.3.7 Synchronous Low-Side FET
      8. 1.3.8 Optional Output Filtering
  3. 2Test Setup and Results
    1. 2.1  Input/Output Connections
    2. 2.2  Efficiency
    3. 2.3  Power Dissipation
    4. 2.4  Output Voltage Regulation
    5. 2.5  Load Transients
    6. 2.6  Loop Characteristic
    7. 2.7  Output Voltage Ripple
    8. 2.8  Input Voltage Ripple
    9. 2.9  Gate Drive
    10. 2.10 Powering Up and Down
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Bill of Materials
  6. 5Revision History

1.3.6 Power Good

An internal circuit monitors the VSENSE input voltage to verify that it is within a guard band around the reference voltage. If these voltages are close to each other in value, and no other fault signals are present, the PWRGD pin presents a high impedance. A low on the PWRGD pin indicates a fault. The PWRGD pin has been designed to provide a weak pulldown and indicates a fault even when the device is unpowered. If the TPS54350 has power and has any fault flag set, the TPS54350 indicates the power is not good by driving the PWRGD pin low. The following events, alone or in combination, indicates power not good:

  • VSENSE pin out of bounds
  • Overcurrent
  • Thermal shutdown
  • UVLO undervoltage
  • Input voltage not present (weak pulldown)
  • Slow starting
  • VBIAS voltage is low

The evaluation module provides an external pullup resistor of 10 kW (R8), a test point TP1 that can be tied to an external 3.3-V or 5-V source, and a test point TP2 to monitor the power-good signal.