SLVUAK9A December   2015  – May 2021 TPS65265

 

  1.   Trademarks
  2. 1Background
  3. 2Schematic
  4. 3Board Layout
  5. 4Bench Test Setup Conditions
    1. 4.1 Header Description and Jumper Placement
  6. 5Power-Up Procedure
  7. 6Bill of Materials
  8. 7Revision History

4.1 Header Description and Jumper Placement

Figure 4-1 shows the jumper and pin placement on the TPS65265EVM-705 board.

GUID-BFC75C98-7FC8-486B-9A4B-E438944BFDBB-low.gifFigure 4-1 TPS65265EVM-705 Header Description and Jumper Placement

Test points:

  1. LX of VOUT1
  2. LX of VOUT2
  3. LX of VOUT3

VOUT1, VOUT2, VOUT3, VIN, PGOOD, PG_DLY, SYNC

Table 4-1 Input/Output Connection
#FunctionDescription
J1Buck1 ConnectorOutput of Buck1
J2Buck2 ConnectorOutput of Buck2
J3Buck3 ConnectorOutput of Buck3
J5VIN ConnectorApply power supply to this connector
Table 4-2 Jumpers
#FunctionPlacementComment
J6Buck1 enable (EN1)Connect EN1 to GND to disable VOUT1

Connect EN1 to HIGH or leave open to enable VOUT1
J7Buck2 enable (EN2)Connect EN2 to GND to disable VOUT2

Connect EN2 to HIGH or leave open to enable VOUT2
J8Buck3 enable (EN3)Connect EN3 to GND to disable VOUT3

Connect EN3 to HIGH or leave open to enable VOUT3
J9MODEPower sequencing mode control pin.

Connect MODE pin to GND or HIGH, set the power sequence with pre-defined power up and power down sequence.

Leave open to set power up and down with dedicated enable pin.