SLVUBX7A June   2020  – November 2020 TPS552882

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Performance Specification
    2. 1.2 Modification
  3. 2Connector, Test Point and Jumper Descriptions
    1. 2.1 Connector and Test Point Descriptions
    2. 2.2 Jumper Configuration
      1. 2.2.1 JP1 (ENABLE)
      2. 2.2.2 JP2(SYNC)
  4. 3Test Procedure
  5. 4Schematic, Bill of Materials, and Board Layout
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
    3. 4.3 Board Layout
  6. 5Revision History

4.3 Board Layout

Figure 4-2 through Figure 4-5 illustrate the EVM board layouts.

GUID-EFC38D9C-2D01-4D34-BD8D-E5A11452A6CA-low.pngFigure 4-2 TPS552882EVM-400kHz Top-Side Layout
GUID-0680A42C-70F1-476A-B724-C58F127FCE71-low.pngFigure 4-3 TPS552882EVM-400kHz Inner Layer1
GUID-2C4E1123-3B69-42ED-8704-833D1E11EBC1-low.pngFigure 4-4 TPS552882EVM-400kHz Inner Layer2
GUID-816CB69D-5CA4-43A0-A64B-51274E445C51-low.png Figure 4-5 TPS552882EVM-400kHz Bottom-Side Layout