SLVUCM3 july   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , TPS6593-Q1

 

  1.   1
  2.   User's Guide for Powering AM62A with TPS65931211-Q1 PMIC
  3.   Trademarks
  4. 1Introduction
  5. 2Device Versions
  6. 3Processor Connections
    1. 3.1 Power Mapping
      1. 3.1.1 Supporting 0.85V on VDD_CORE
      2. 3.1.2 Using 5V Input Supply
    2. 3.2 Control Mapping
  7. 4Supporting Functional Safety ASIL-B Requirements
  8. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  9. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 Sequence: immediateOff2Safe_pd
      2. 6.3.2 Sequence: orderlyOff2safe
      3. 6.3.3 Sequence: warmReset
      4. 6.3.4 Sequence: any2active
      5. 6.3.5 Sequence: any2_s2r
  10. 7Application Examples
    1. 7.1 Entering and Exiting S2R (Suspend to RAM)
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
  11. 8References

3.2 Control Mapping

Figure 3-2 shows the digital control signal mapping between processor and PMIC. Specific GPIO pins have been assigned to key signals in order to ensure proper operation. The digital connections allow system features including Partial IO, I/O + DDR, functional safety up to ASIL-B, and compliant dual voltage SD card operation. GPIO4 was configured as push-pull output to enable the external 3.3V power-switch at the beginning of the sequence.

GPIO9 and GPIO11 are configured to enable LDO2 (VPP) and LDO1 (SD card interface). The TPS65931211-Q1 enables LDO1 when a rising edge is detected on GPIO11 after nRSTOUT is released and PMIC is in Active state. Similarly, the PMIC enables LDO2 when a rising edge is detected on GPO9 after nRSTOUT is released.

GPIO5, GPIO6 and GPIO10 are configured to set the output voltages on some of the PMIC power resources and the state (high or low) for these GPIOs need to be set before the assigned rail turns ON. GPIO5 is configured to set the output voltage on LDO1 to support UHS-I SD cards (3.3V or 1.8V). GPIO6 is configured to set the voltage on the multiphase Buck1/2/3 to support either VDD_CORE voltage (0.75V or 0.85V). GPIO10 is configured to set the voltage on Buck4 to support LPDDR4 (1.1V) or DDR4 (1.2V).

The PMIC_LPM_EN0 on the AM62A processor is a dual function control signal used to trigger a Low Power Mode (active low) or PMIC enable (active high). This signal drives the PMIC GPIO3 (nSLEEP2) when triggering IO+DDR mode (suspend to RAM). Alternatively, the PMIC_LPM_EN0 signal can drive the PMIC enable pin when triggering Partial IO low power mode.

GUID-20221110-SS0I-FHML-S1BG-TQ5XX8KXTSVT-low.svg Figure 3-2 TPS65931211-Q1 Digital Connections
Note: PMIC IO can have distinct power domains for input and output functionality. The SDA function for I2C1 and I2C2 use the VINT voltage domain as an input and the VIO voltage domain as an output. When configured as an input GPIO3 is in the VRTC domain. When configured as an output, GPIO4 is in the VINT domain. Please refer to the device data sheet for a complete description.

Table 3-2 shows the digital signals on the TPS65931211-Q1 that were configured as open drain and the AM62A domain they must be pulled up to.

Table 3-2 Open-drain signals and AM62 Power Domain
PMIC open drain signal AM62A signal name AM62A Power Domain
nINT EXTINTn VDDSHV0
nRSTOUT MCU_PORz VDDS_OSC (1.8V)
SCL_I2C1 I2C0_SCL VDDSHV0
SDA_I2C1 I2C0_SDA VDDSHV0
GPIO1 (SCL_I2C2) MCU_I2C0_SCL VDDSHV_MCU
GPIO2 (SDA_I2C2) MCU_I2C0_SDA VDDSHV_MCU

Please use Table 3-3 as a guide to understand GPIO assignments required for each PDN system feature. If the feature listed is not required, the digital connection can be removed; however, the GPIO pin is still configured per NVM defined default function shown. After the processor has booted up, the processor can reconfigure unused GPIOs to support new functions. Reconfiguring a GPIO function is possible as long as that function is only needed after boot and default function does not cause any conflicts with normal operations (for example, two outputs driving same net).

Table 3-3 Digital Connections by System Feature
Device GPIO Mapping System Features(2)
PMIC Pin NVM Function Active SoC Functional Safety IO + DDR SD Card
TPS65931211-Q1 nPWRON/ ENABLE Enable R R
INT INT R R
nRSTOUT nRSTOUT R
SCL_I2C1 SCL_I2C1 R
SDA_I2C1 SDA_I2C1 R
GPIO_1 SCL_I2C2 R
GPIO_2 SDA_I2C2 R
GPIO_3 nSLEEP2 R
GPIO_4 GPO

(enables 3.3V power-switch)

 R
GPIO_5 GPI

(sets output voltage on LDO1)

 O (3) R
GPIO_6 GPI

(sets output voltage on BUCK1/2/3)

 R
GPIO_7 nERR_MCU R
GPIO_8 DISABLE_WDOG O (1)
GPIO_9 GPI

(enables/disables LDO2)
GPIO_10 GPI

(sets output voltage on BUCK4)

 R
GPIO_11 GPI

(enables/disables LDO1)

 R
(1) If it is desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high. After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software.
(2) R is Required. O is optional.
(3) GPIO5 from the PMIC does not need to be connected to the processor if LDO1 is not used to supply the uSD card interface.