Product details

Arm CPU 2 Arm Cortex-A53, 4 Arm Cortex-A53 Arm (max) (MHz) 1400 Coprocessors 1 Arm Cortex-R5F CPU 64-bit Display type MIPI DPI Protocols Ethernet, TSN Ethernet MAC 2-Port 10/100/1000 Hardware accelerators 1 deep learning accelerator, 1 video encode/decode accelerator, 1 vision pre-processing accelerator Features Vision Analytics Operating system Linux, RTOS Security Secure boot TI functional safety category Functional Safety-Compliant Rating Automotive, Catalog Operating temperature range (°C) -40 to 125
Arm CPU 2 Arm Cortex-A53, 4 Arm Cortex-A53 Arm (max) (MHz) 1400 Coprocessors 1 Arm Cortex-R5F CPU 64-bit Display type MIPI DPI Protocols Ethernet, TSN Ethernet MAC 2-Port 10/100/1000 Hardware accelerators 1 deep learning accelerator, 1 video encode/decode accelerator, 1 vision pre-processing accelerator Features Vision Analytics Operating system Linux, RTOS Security Secure boot TI functional safety category Functional Safety-Compliant Rating Automotive, Catalog Operating temperature range (°C) -40 to 125
FCBGA (AMB) 484 324 mm² 18 x 18

Processor Cores:

  • Up to Quad Arm Cortex-A53 microprocessor subsystem at up to 1.4 GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800 MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800 MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Deep Learning Accelerator based on Single-core C7x
    • C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at 1.0 GHz
    • Matrix Multiply Accelerator (MMA), up to 2 TOPS (8b) at 1.0 GHz
    • 32KB L1 DCache with SECDED ECC and 64KB L1 ICache with Parity protection
    • 1.25MB of L2 SRAM with SECDED ECC
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
    • 315 MPixel/s ISP; Up to 5MP @ 60 fps
    • Support for 12-bit RGB-IR
    • Support for up to 16-bit input RAW format
    • Line support up to 4096
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
      • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem
    • Single display support
    • Up to 2048x1080 @ 60fps
    • Up to 165-MHz pixel clock support with independent PLL
    • DPI 24-bit RGB parallel interface
    • Supports safety features such as freeze frame detection and MISR data check
  • One Camera Serial interface (CSI-2) Receiver with 4-Lane D-PHY
    • MIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
    • Support for 1,2,3 or 4 data lane mode up to 1.5 Gbps per lane
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Clocking options supporting 240 MPixels/s, 120 MPixels/s, or 60 MPixels/s
  • Motion JPEG encode at 416 MPixels/s with resolutions up to 4K UHD (3840 × 2160)

Memory Subsystem:

  • Up to 2.29MB of On-chip RAM
    • 64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
    • 1.25MB of L2 SRAM with SECDED ECC in C7x Deep Learning Accelerator
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4
    • 32-bit data bus with inline ECC
    • Supports speeds up to 3733 MT/s
    • Max addressable range of 8GBytes

Functional Safety:

  • Functional Safety-Compliant targeted [Industrial]
    • Developed for functional safety applications
    • Documentation will be available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3 targeted
    • Hardware Integrity up to SIL 2 targeted
    • Safety-related certification
      • IEC 61508 by TÜV SÜD planned
  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 by TÜV SÜD planned
  • AEC-Q100 qualified [Automotive]

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • Two USB2.0 Ports
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 6x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50 MHz
    • Up to 16/10/6 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 3x Controller Area Network (CAN) modules with CAN-FD support
    • Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
    • Full CAN FD support (up to 64 data bytes)
    • Parity/ECC check for Message RAM
    • Speed up to 8 Mbps

Media and Data Storage:

  • 3x Secure Digital (SD) (4b+4b+8b) interface
    • 1x 8-bit eMMC interface up to HS200 speed
    • 2x 4-bit SD/SDIO interface up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133 MHz
    • Flexible 8- and 16-bit Asynchronous Memory Interface with up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH code to support 4-, 8-, or 16-bit ECC
    • Uses Hamming code to support 1-bit ECC
    • Error Locator Module (ELM)
      • Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
      • Supports 4-, 8-, and 16-bit per 512-Byte block error location based on BCH algorithms
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash devices
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Power Management:

  • Low-power modes supported by Device/Power Manager
    • Partial IO support for CAN/GPIO/UART wakeup
    • DeepSleep : I/O + DDR (suspend to RAM)
    • DeepSleep
    • MCU Only
    • Standby
    • Dynamic frequency scaling for Cortex-A53

Boot Options:

  • UART
  • I2C EEPROM
  • OSPI/QSPI Flash
  • GPMC NOR/NAND Flash
  • SD Card
  • eMMC
  • USB (host) Mass storage
  • USB (device) boot from external host (DFU mode)
  • Ethernet

Technology / Package:

  • 16-nm FinFET technology
  • 18 mm x 18 mm, 0.8-mm pitch full-array, 484-pin FCBGA (AMB)

Processor Cores:

  • Up to Quad Arm Cortex-A53 microprocessor subsystem at up to 1.4 GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800 MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800 MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Deep Learning Accelerator based on Single-core C7x
    • C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at 1.0 GHz
    • Matrix Multiply Accelerator (MMA), up to 2 TOPS (8b) at 1.0 GHz
    • 32KB L1 DCache with SECDED ECC and 64KB L1 ICache with Parity protection
    • 1.25MB of L2 SRAM with SECDED ECC
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
    • 315 MPixel/s ISP; Up to 5MP @ 60 fps
    • Support for 12-bit RGB-IR
    • Support for up to 16-bit input RAW format
    • Line support up to 4096
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
      • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem
    • Single display support
    • Up to 2048x1080 @ 60fps
    • Up to 165-MHz pixel clock support with independent PLL
    • DPI 24-bit RGB parallel interface
    • Supports safety features such as freeze frame detection and MISR data check
  • One Camera Serial interface (CSI-2) Receiver with 4-Lane D-PHY
    • MIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
    • Support for 1,2,3 or 4 data lane mode up to 1.5 Gbps per lane
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Clocking options supporting 240 MPixels/s, 120 MPixels/s, or 60 MPixels/s
  • Motion JPEG encode at 416 MPixels/s with resolutions up to 4K UHD (3840 × 2160)

Memory Subsystem:

  • Up to 2.29MB of On-chip RAM
    • 64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
    • 1.25MB of L2 SRAM with SECDED ECC in C7x Deep Learning Accelerator
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4
    • 32-bit data bus with inline ECC
    • Supports speeds up to 3733 MT/s
    • Max addressable range of 8GBytes

Functional Safety:

  • Functional Safety-Compliant targeted [Industrial]
    • Developed for functional safety applications
    • Documentation will be available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3 targeted
    • Hardware Integrity up to SIL 2 targeted
    • Safety-related certification
      • IEC 61508 by TÜV SÜD planned
  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 by TÜV SÜD planned
  • AEC-Q100 qualified [Automotive]

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • Two USB2.0 Ports
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 6x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50 MHz
    • Up to 16/10/6 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 3x Controller Area Network (CAN) modules with CAN-FD support
    • Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
    • Full CAN FD support (up to 64 data bytes)
    • Parity/ECC check for Message RAM
    • Speed up to 8 Mbps

Media and Data Storage:

  • 3x Secure Digital (SD) (4b+4b+8b) interface
    • 1x 8-bit eMMC interface up to HS200 speed
    • 2x 4-bit SD/SDIO interface up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133 MHz
    • Flexible 8- and 16-bit Asynchronous Memory Interface with up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH code to support 4-, 8-, or 16-bit ECC
    • Uses Hamming code to support 1-bit ECC
    • Error Locator Module (ELM)
      • Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
      • Supports 4-, 8-, and 16-bit per 512-Byte block error location based on BCH algorithms
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash devices
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Power Management:

  • Low-power modes supported by Device/Power Manager
    • Partial IO support for CAN/GPIO/UART wakeup
    • DeepSleep : I/O + DDR (suspend to RAM)
    • DeepSleep
    • MCU Only
    • Standby
    • Dynamic frequency scaling for Cortex-A53

Boot Options:

  • UART
  • I2C EEPROM
  • OSPI/QSPI Flash
  • GPMC NOR/NAND Flash
  • SD Card
  • eMMC
  • USB (host) Mass storage
  • USB (device) boot from external host (DFU mode)
  • Ethernet

Technology / Package:

  • 16-nm FinFET technology
  • 18 mm x 18 mm, 0.8-mm pitch full-array, 484-pin FCBGA (AMB)

AM62Ax is an extension of the Sitara™ automotive-grade family of heterogeneous Arm® processors with embedded Deep Learning (DL), Video and Vision Processing acceleration, display interface and extensive automotive peripheral and networking options. AM62Ax is built for a set of cost-sensitive automotive applications including driver and in-cabin monitoring systems, next generation of eMirror system, as well as a broad set of industrial applications in Factory Automation, Building Automation, and other markets. The cost optimized AM62Ax provides high-performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in stand-alone Electronic Control Units (ECUs).

AM62Ax contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL) and video accelerators, a Cortex®-R5F MCU Channel core and a Cortex®-R5F Device Management core. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based-algorithms such as driver monitoring. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include the next generation C7000™ DSP from Texas Instruments (“C7x”) with scalar and vector cores, dedicated “MMA” deep learning accelerator enabling performance up to 2 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.

The 3-port Gigabit Ethernet switch has one internal port and two external ports with TSN support and can be used to enable industrial networking options. In addition, an extensive peripherals set is included in AM62Ax to enable system level connectivity such as USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. AM62Ax supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and also employs advanced power management support for portable and power-sensitive applications.

AM62Ax is an extension of the Sitara™ automotive-grade family of heterogeneous Arm® processors with embedded Deep Learning (DL), Video and Vision Processing acceleration, display interface and extensive automotive peripheral and networking options. AM62Ax is built for a set of cost-sensitive automotive applications including driver and in-cabin monitoring systems, next generation of eMirror system, as well as a broad set of industrial applications in Factory Automation, Building Automation, and other markets. The cost optimized AM62Ax provides high-performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in stand-alone Electronic Control Units (ECUs).

AM62Ax contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL) and video accelerators, a Cortex®-R5F MCU Channel core and a Cortex®-R5F Device Management core. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based-algorithms such as driver monitoring. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include the next generation C7000™ DSP from Texas Instruments (“C7x”) with scalar and vector cores, dedicated “MMA” deep learning accelerator enabling performance up to 2 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.

The 3-port Gigabit Ethernet switch has one internal port and two external ports with TSN support and can be used to enable industrial networking options. In addition, an extensive peripherals set is included in AM62Ax to enable system level connectivity such as USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. AM62Ax supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and also employs advanced power management support for portable and power-sensitive applications.

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Technical documentation

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Type Title Date
* Data sheet AM62Ax Sitara™ Processors datasheet PDF | HTML 01 Sep 2021
* Errata AM62Ax Sitara™ Processors Silicon Errata, Silicon Revision 1.0 PDF | HTML 26 Apr 2022
White paper Easing the Pain of Safety Certified System Development PDF | HTML 24 May 2023
Application note Building an Edge AI Application for Automated Retail Scanner on AM6xA MPUs PDF | HTML 17 May 2023
Application note AM625/AM623 and AM62A7/AM62A3 Schematic Design and Review Checklist (Rev. B) PDF | HTML 08 May 2023
User guide AM62Ax Sitara Processors Technical Reference Manual (Rev. A) 06 Apr 2023
Application note AM62Ax Maximum Current Ratings PDF | HTML 30 Mar 2023
Application note Hardware Design Guide for AM62A Devices PDF | HTML 30 Mar 2023
Technical article How vision processors are expanding edge AI capabilities in video doorbell and smart retail designs 15 Mar 2023
Application note AM6xA ISP Tuning Guide PDF | HTML 02 Mar 2023
White paper Edge AI Smart Cameras Using Energy-Efficient AM62A Processor PDF | HTML 02 Mar 2023
Application note Sitara™AM62A Benchmarks PDF | HTML 01 Mar 2023
Application note AM62Ax DDR Board Design and Layout Guidelines PDF | HTML 27 Feb 2023
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 24 Feb 2023
Application note AM62Ax Power-Estimation Tool (PET)-- PDF | HTML 23 Feb 2023
User guide AM62Ax Escape Routing for PCB Design PDF | HTML 05 Dec 2022
Technical article How to simplify your embedded edge AI application development 28 Jan 2022
User guide AM62Ax Sitara Processors Technical Reference Manual 15 Jul 2021

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

SK-AM62A-LP — AM62A starter kit for low-power Sitara™ processors

The SK-AM62A-LP starter kit (SK) evaluation module (EVM) is built around our AM62A AI vision processor, which includes an image signal processor (ISP) supporting up to 5 MP at 60 fps, a 2 teraoperations per second (TOPS) AI accelerator, a quad-core 64-bit Arm® Cortex®-A53 microprocessor, a (...)

User guide: PDF | HTML
Not available on TI.com
Debug probe

TMDSEMU560V2STM-U — XDS560™ software v2 system trace USB debug probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com
Software development kit (SDK)

MCU-PLUS-SDK-AM62A MCU+ SDK for AM62A – RTOS, No-RTOS

The AM62A vision processor Linux® and TI MCU plus software development kits (SDKs) are unified software platforms for our embedded processors with deep learning capabilities with edge AI. They provide easy setup and fast out-of-the-box access to benchmarks and demonstrations. AM62A is a high (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
AM62A3 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power, video surveillance, retail automation AM62A3-Q1 Automotive 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, dashcams AM62A7 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power systems, machine vision, robotics AM62A7-Q1 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras
Hardware development
Evaluation board
SK-AM62A-LP AM62A starter kit for low-power Sitara™ processors
Browse Download options
Software development kit (SDK)

PROCESSOR-SDK-LINUX-AM62A Linux SDK for edge AI applications on AM62A

The AM62A vision processor Linux® and TI MCU plus software development kits (SDKs) are unified software platforms for our embedded processors with deep learning capabilities with edge AI. They provide easy setup and fast out-of-the-box access to benchmarks and demonstrations. AM62A is a high (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
AM62A3 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power, video surveillance, retail automation AM62A3-Q1 Automotive 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, dashcams AM62A7 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power systems, machine vision, robotics AM62A7-Q1 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras
Hardware development
Evaluation board
SK-AM62A-LP AM62A starter kit for low-power Sitara™ processors
Download options
Software development kit (SDK)

PROCESSOR-SDK-LINUX-RT-AM62A RT-Linux SDK for edge AI applications on AM62A

The AM62A vision processor Linux® and TI MCU plus software development kits (SDKs) are unified software platforms for our embedded processors with deep learning capabilities with edge AI. They provide easy setup and fast out-of-the-box access to benchmarks and demonstrations. AM62A is a high (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
AM62A3 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power, video surveillance, retail automation AM62A3-Q1 Automotive 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, dashcams AM62A7 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power systems, machine vision, robotics AM62A7-Q1 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras
Hardware development
Evaluation board
SK-AM62A-LP AM62A starter kit for low-power Sitara™ processors
Download options
IDE, configuration, compiler or debugger

C7000-CGT C7000 code generation tools (CGT) - compiler

The TI C7000 C/C++ Compiler Tools support development of applications for TI C7000 Digital Signal Processor cores.

Code Composer Studio is the Integrated Development Environment (IDE) for TI embedded devices.  If you are looking to develop on a TI embedded device it is recommended to start (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
TDA4VM Dual Arm® Cortex®-A72 SoC and C7x DSP with deep-learning, vision and multimedia accelerators TDA4VM-Q1 Automotive system-on-a-chip for L2, L3 and near-field analytic systems using deep learning AM62A3 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power, video surveillance, retail automation AM62A7 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power systems, machine vision, robotics AM62A3-Q1 Automotive 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, dashcams AM62A7-Q1 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras AM69A 32 TOPS vision SoC for 1-12 cameras, Autonomous Mobile Robots, Machine Vision, Mobile DVR, AI-BOX AM68A 8 TOPS vision SoC for 1-8 cameras, machine vision, smart traffic, retail automation
Download options
IDE, configuration, compiler or debugger

C7000-SAFETI-CQKIT-RV C7000 safety compiler qualification kit (leverages compiler release validations)

The Safety Compiler Qualification Kit was developed to assist customers in qualifying their use of the TI ARM, C6000, C7000 or C2000/CLA C/C++ Compiler to functional safety standards such as IEC 61508 and ISO 26262.

The Safety Compiler Qualification Kit:

  • is free of charge for TI customers
  • does (...)
Supported products & hardware

Supported products & hardware

Products
Arm-based processors
TDA4VM-Q1 Automotive system-on-a-chip for L2, L3 and near-field analytic systems using deep learning AM62A3 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power, video surveillance, retail automation AM62A7 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power systems, machine vision, robotics AM62A3-Q1 Automotive 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, dashcams AM62A7-Q1 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras
Download options
IDE, configuration, compiler or debugger

CCSTUDIO Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

Supported products & hardware

Supported products & hardware

This design resource supports most products in these categories.

Check the product details page to verify support.

Products
Automotive mmWave radar sensors
AWR1243 76-GHz to 81-GHz high-performance automotive MMIC AWR1443 Single-chip 76-GHz to 81-GHz automotive radar sensor integrating MCU and hardware accelerator AWR1642 Single-chip 76-GHz to 81-GHz automotive radar sensor integrating DSP and MCU AWR1843 Single-chip 76-GHz to 81-GHz automotive radar sensor integrating DSP, MCU and radar accelerator AWR1843AOP Single-chip 76-GHz to 81-GHz automotive radar sensor integrating antenna on package, DSP and MCU AWR2243 76-GHz to 81-GHz automotive second-generation high-performance MMIC AWR2944 Automotive 2nd-generation, 76-GHz to 81-GHz, high-performance SoC for corner and long-range radar AWR6443 Single-chip 60-GHz to 64-GHz automotive radar sensor integrating MCU and radar accelerator AWR6843 Single-chip 60-GHz to 64-GHz automotive radar sensor integrating DSP, MCU and radar accelerator AWR6843AOP Single-chip 60-GHz to 64-GHz automotive radar sensor integrating antenna on package, DSP and MCU
Industrial mmWave radar sensors
IWR1443 Single-chip 76-GHz to 81-GHz mmWave sensor integrating MCU and hardware accelerator IWR1642 Single-chip 76-GHz to 81-GHz mmWave sensor integrating DSP and MCU IWR1843 Single-chip 76-GHz to 81-GHz industrial radar sensor integrating DSP, MCU and radar accelerator IWR6443 Single-chip 60-GHz to 64-GHz intelligent mmWave sensor integrating MCU and hardware accelerator IWR6843 Single-chip 60-GHz to 64-GHz intelligent mmWave sensor integrating processing capability IWR6843AOP Single-chip 60-GHz to 64-GHz intelligent mmWave sensor with integrated antenna on package (AoP)
Launch Download options
IDE, configuration, compiler or debugger

EDGE-AI-STUDIO Edge AI studio

Edge AI Studio is a collection of tools aimed to accelerate the development of edge AI application on TI embedded devices.

Model Analyzer, formerly known as TI edge AI cloud, is a free online service that allows for the evaluation of accelerated deep learning inference on remotely accessed (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
AM62A3 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power system, video doorbell, security camera AM62A3-Q1 Automotive 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, dashcams AM62A7 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power systems, video surveillance, lawn robot AM62A7-Q1 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras AM68A 8 TOPS vision SoC for 1-8 cameras, machine vision, smart traffic, retail automation AM69A 32 TOPS vision SoC for 1-12 cameras, Autonomous Mobile Robots, Machine Vision, Mobile DVR, AI-BOX TDA4VM Dual Arm® Cortex®-A72 SoC and C7x DSP with deep-learning, vision and multimedia accelerators TDA4VM-Q1 Automotive system-on-a-chip for L2, L3 and near-field analytic systems using deep learning
Hardware development
Evaluation board
J721EXCPXEVM Common processor board for Jacinto™ 7 processors J721EXSOMXEVM TDA4VM and DRA829V socketed system on module (SoM) SK-TDA4VM TDA4VM processor starter kit for edge AI vision systems SK-AM62A-LP AM62A starter kit for low-power Sitara™ processors SK-AM68 AM68x starter kit for Sitara™ processors SK-AM69 Starter kit for Sitara™ processors
Software
Software development kit (SDK)
PROCESSOR-SDK-AM62A Software development kit for AM62A Sitara™ processors for edge AI applications
Support software
PROCESSOR-SDK-AM68A Software development kit for AM68A processors PROCESSOR-SDK-AM69A Software development kit for AM69A processors
Simulation model

AM62Ax Sitara™ AMI Model

SPRM784.ZIP (30672 KB) - IBIS-AMI Model
Simulation model

AM62Ax Sitara™ BSDL Model

SPRM786.ZIP (10 KB) - BSDL Model
Simulation model

AM62Ax Sitara™ IBIS Model

SPRM785.ZIP (3291 KB) - IBIS Model
Simulation model

AM62Ax Sitara™ Thermal Model

SPRM787.ZIP (4875 KB) - Thermal Model
Assembly drawing

SK-AM62A-LP Design File Package (Rev. A)

SPRR459A.ZIP (31633 KB)
Calculation tool

AM62X-PET-CALC — AM62x power-estimation tool (PET)

The AM62x power-estimation tool (PET) spreadsheet allows the user to calculate power consumption estimates based on measured and simulated data. Estimates are provided as is and are not ensured within a specified precision. Power consumption depends on electrical parameters, silicon process (...)
Design tool

PROCESSORS-3P-SEARCH — Arm®-based MPU, Arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
Package Pins Download
FCBGA (AMB) 484 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

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