SLVUD97 September 2026
By default, the TSWDC155EVM provides the ADS9308V8IEVM with a 3.3V supply (3P3V). The ADS9308V8IEVM has a TPS61070 boost converter that boosts the 3.3V supply to 5.4V. By default, this voltage is applied to low-dropout regulators (LDOs) to derive the AVDD_5V, AVDD_1V8, and IOVDD supplies when JP1 is in the [1-2] position. U5 (TPS7A2050) provides the 5V AVDD_5V supply, U6 (TPS7A2018) provides the AVDD_1V8 supply, and U4 (TPS7A2033) provides 3.3V for IOVDD, respectively. The LDO input voltage can be changed to an external source (5.2V to 5.5V) applied to terminal block J7 by placing a shunt on JP1 in the [2-3] position. In this case, U3 (LM66100) provides reverse polarity protection if the connection is wired incorrectly.
IOVDD can be either 1.8V or 3.3V. This allows ADS9308V8I the interface with both FPGAs and MCUs.
To set the IOVDD = 1.8V on the EVM:
To set the IOVDD = 3.3V on the EVM:
Figure 2-7 shows the power tree schematic for the ADS9308V8IEVM.