SLVUDE1 July 2025 TPS65219-Q1
This section describes the PMIC rails that are enabled in Active and Standby state. Any rail that is disabled by default has the option to be enabled through I2C once the device is in Active state and I2C communication is available. The transition between Active and Standby state can be triggered by hardware (when MODE/STBY pin is configured as STBY) or by software (register field: STBY_I2C_CTRL).
| PMIC Rail | Register Address | Field Name | Value | Description |
|---|---|---|---|---|
| BUCK1 | 0x02 | BUCK1_EN | 0x1 | Enabled |
| BUCK2 | 0x02 | BUCK2_EN | 0x1 | Enabled |
| BUCK3 | 0x02 | BUCK3_EN | 0x1 | Enabled |
| LDO1 | 0x02 | LDO1_EN | 0x1 | Enabled |
| LDO2 | 0x02 | LDO2_EN | 0x1 | Enabled |
| LDO3 | 0x02 | LDO3_EN | 0x1 | Enabled |
| LDO4 | 0x02 | LDO4_EN | 0x1 | Enabled |
| GPO1 | 0x1E | GPO1_EN | 0x0 | GPO1 disabled. The output state is low. |
| GPO2 | 0x1E | GPO2_EN | 0x1 | GPO2 enabled. The output state is Hi-Z. |
| GPIO | 0x1E | GPIO_EN | 0x0 | GPIO disabled. The output state is low. |
| PMIC Rail | Register Address | Field Name | Value | Description |
|---|---|---|---|---|
| BUCK1 | 0x21 | BUCK1_STBY_EN | 0x1 | Enabled in STBY Mode |
| BUCK2 | 0x21 | BUCK2_STBY_EN | 0x1 | Enabled in STBY Mode |
| BUCK3 | 0x21 | BUCK3_STBY_EN | 0x1 | Enabled in STBY Mode |
| LDO1 | 0x21 | LDO1_STBY_EN | 0x1 | Enabled in STBY Mode |
| LDO2 | 0x21 | LDO2_STBY_EN | 0x1 | Enabled in STBY Mode |
| LDO3 | 0x21 | LDO3_STBY_EN | 0x1 | Enabled in STBY Mode |
| LDO4 | 0x21 | LDO4_STBY_EN | 0x1 | Enabled in STBY Mode |
| GPO1 | 0x22 | GPO1_STBY_EN | 0x0 | Disabled in STBY Mode |
| GPO2 | 0x22 | GPO2_STBY_EN | 0x1 | Enabled in STBY Mode |
| GPIO | 0x22 | GPIO_STBY_EN | 0x0 | Disabled in STBY Mode |