SLVUE53 October   2026

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Setup
    3. 2.3 Header Information
    4. 2.4 Jumper Information
    5. 2.5 Test Points
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  10. 4Additional Information
    1. 4.1 Trademarks

2.3 Header Information

Table 2-1 details header information for three sections of the board. Optional power connections to an external DAC or MCU are provided for each XTR102 and XTR120 section. Each section is partitioned as a separate board and signals are isolated between the different sections. Power and GND must not be mixed between the different board sections.

Table 2-1 Header Information
SectionHeaderFunction
XTR100J3Loop power: LOOP+, LOOP-
J4Input signal: VIN, GND
XTR102J6Input signal: VIN, GND

HART interface: HART_Rx, HART_Tx

Output power (optional): VCC, VREF

J8Loop power: LOOP+, LOOP-
XTR120J13Loop power: LOOP+, LOOP-
J14Input signal: PWM_IN, GND

HART interface: HART_Rx, HART_Tx

Output power (optional): VCC