SLVZ025 March   2022 LP8764-Q1

 

  1. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  2. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  3. 3Silicon Revision 2.0 Usage Notes and Advisories
  4. 4Silicon Revision 2.0 Usage Notes
  5. 5Silicon Revision 2.0 Advisories
    1. 5.1 Advisories
  6. 6Trademarks

1.2 Advisories Matrix

Table 1-1 Advisories Matrix
MODULE DESCRIPTION SILICON REVISIONS AFFECTED
2.0
Serial Peripheral Interface SDO_SPI signal falling edge slew-rate is reduced X
Built-in Self Test Voltage monitor Analog-BIST may cause false over voltage and under voltage interrupts X
Serial Peripheral Interface SPI Frame Error is generated during device startup if CS_SPI-pin is low X
Built-in Self Test Under voltage and short circuit detection comparators are gated for a short period after Runtime BIST is completed X
State-machine LP_STANDBY-state quiescent current consumption is ~3 mA X
Error Signal Monitor Error Signal Monitoring (ESM) Fail Interrupt (ESM_MCU_FAIL_INT) operation in level mode operation X
Serial Peripheral Interface SPI Frame Error is not detected if SCK_SPI has additional rising edge at the end of communication and the number of clock falling edges is correct X
Register Map SOFT_REBOOT bit protection X
GPIOs EN_DRV(GPIO1) cannot drive high when VCCA and VIO voltages are different X
Built-in Self Test PGOOD signal can be errornously inactive during runtime BIST X