SLWU094 March 2021
The TSW14J58 EVM has one connector to allow for the direct plug in of TI JESD204C_B serial interface ADC and DAC EVMs. The specifications for this connector are mostly derived from the ANSI/VITA 57.4 FPGA Mezzanine Card (FMC+) Standard. This standard describes the compliance requirements for a low-overhead protocol bridge between the IO of a mezzanine card and an FPGA processing device on a carrier card. This specification is being used by FPGA vendors on their development platforms.
The FMC+ connector, J3, provides the interface between the TSW14J58EVM and the ADC or DAC EVM under test. This 560-pin Samtec high-speed, high-density connector (part number ASP-184329-01) is suitable for high-speed differential pairs up to 32.5 Gbps.
In addition to the JESD204B/C standard signals, several CMOS single-ended signals and LVDS differential signals are connected between the FMC+ and FPGA. In the future, these signals may allow the HSDC Pro GUI to control the SPI serial programming of ADC and DAC EVMs that support this feature. The connector pinout description is shown in Table 3-5.
| FMC+ Signal Name | FMC+ Pin | Standard JESD204 Application Mapping | Description |
|---|---|---|---|
| RXP/N0_0 | C6 and C7 | Lane 0± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RXP/N1_0 | A2 and A3 | Lane 1± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RXP/N2_0 | A6 and A7 | Lane 2± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RXP/N3_0 | A10 and A11 | Lane 3± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RXP/N0_1 | A14 and A15 | Lane 4± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RXP/N1_1 | A18 and A19 | Lane 5± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RXP/N2_1 | B16 and B17 | Lane 6± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RXP/N3_1 | B12 and B13 | Lane 7± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RXP/N0_2 | B8 and B9 | Lane 8± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RXP/N1_2 | B4 and B5 | Lane 9± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RXP/N2_2 | Y10 and Y11 | Lane 10± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RXP/N3_2 | Z12 and Z13 | Lane 11± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RXP/N0_3 | Y14 and Y15 | Lane 12± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RXP/N1_3 | Z16 and Z17 | Lane 13± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RXP/N2_3 | Y18 and Y19 | Lane 14± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RXP/N3_3 | Y22 and Y23 | Lane 15± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| TXP/N0_0 | C2 and C3 | Lane 0± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TXP/N1_0 | A22 and A23 | Lane 1± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TXP/N2_0 | A26 and A27 | Lane 2± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TXP/N3_0 | A30 and A31 | Lane 3± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TXP/N0_1 | A34 and A35 | Lane 4± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TXP/N1_1 | A38 and A39 | Lane 5± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TXP/N2_1 | B36 and B37 | Lane 6± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TXP/N3_1 | B32 and B33 | Lane 7± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TXP/N0_2 | B28 and B29 | Lane 8± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TXP/N1_2 | B24 and B25 | Lane 9± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TXP/N2_2 | Z24 and Z25 | Lane 10± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TXP/N3_2 | Y26 and Y27 | Lane 11± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TXP/N0_3 | Z28 and Z29 | Lane 12± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TXP/N1_3 | Y30 and Y31 | Lane 13± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TXP/N2_3 | Z8 and Z9 | Lane 14± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TXP/N3_3 | Y6 and Y7 | Lane 15± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| J3_REFCLKP/N0_0 | D4 and D5 | DEVCLKA± (M → C) | Primary carrier-bound reference clock required for FPGA giga-bit transceivers. Equivalent to device clock. |
| J3_REFCLKP/N1_0 | B20 and B21 | Alt. DEVCLKA± (M → C) | Alternate Primary Carrier-bound reference clock required for FPGA giga-bit transceivers. For use when DEVCLKA (M → C) is not available |
| J3_REFCLKP/N1_1 | Z20 and Z21 | Alt. DEVCLKA+ (M → C) | Alternate Primary Carrier-bound reference clock required for FPGA giga-bit transceivers. For use when DEVCLKA (M → C) is not available |
| Device Clock, SYSREF, and SYNC | |||
|
GPIO_DIFF_P/N<9> |
G6 and G7 | DEVCLKB± (M → C) | Secondary carrier-bound device clock. Used for special FPGA functions such as sampling SYSREF |
| GPIO_DIFF_P/N<3> | G9 and G10 | SYSREF± (M → C) | Carrier-bound SYSREF signal |
| GPIO_DIFF_P/N<2> | G12 and G13 | SYNC± (C → M) | ADC mezzanine-bound SYNC signal for use in class 0/1/2 JESD204 systems |
|
AC14_P/N |
F10 and F11 | DAC SYNC± (M → C) | Carrier-bound SYNC signal for use in class 0/1/2 JESD204B systems |
| GPIO_DIFF_P/N<9> | F19 and F20 | Alt. DAC SYNC± (M → C) | Alternate carrier-bound SYNC signal for use in class 0/1/2 JESD204B systems |
| GPIO_DIFF_P/N<9> | H31 and H32 | Alt. SYNC± (C → M) | Alternate ADC mezzanine-bound SYNC signal. For use when SYNC (C → M) is not available |
| Special Purpose I/O | |||
| GPIO_C6 | F1 |
Spare from FPGA pin G25 |
|
| GPIO_C3 | K10 |
Spare from FPGA pin U24 |
|
| GPIO_C5 | K14 | Spare from FPGA pin AF13 | |
| GPIO_C10 | K7 | Spare from FPGA pin AF15 | |
| GPIO_B25 | K13 | Spare from FPGA pin AE13 | |
| GPIO_B26 | K11 | Spare from FPGA pin Y23 | |
| GPIO_D15 | K8 | Spare from FPGA pin Y16 | |
| ACLK | D11 | Spare from FPGA pin W12 | |
| ASDIO | D12 | Spare from FPGA pin W13 | |
| PRESENT | H2 | Present | USB2.0 input. Indicates if a mezzanine card is present |
| ASDO | D26 | Spare from FPGA pin G11 | |
| ASEN | D27 | Spare from FPGA pin G9 | |
| PRESENT_Z1 | Z1 | Present | USB2.0 input. Indicates if a mezzanine card is present. |
| K4_P/K4_N | K4 and K5 | REFCLKP1_3 to FPGA pin H7 and H6 | |
| CSB_ADC | D17 | Spare from FPGA pin AA13 | |
| CSB_LMK | D18 | Spare from FPGA pin AF13 | |
| CSB_LMX | D20 | Spare from FPGA pin AF14 | |
| SCLK | C22 | Spare from FPGA pin W12 | |
| SDI | C23 | Spare from FPGA pin W13 | |
| SDO_ADC | C26 | Spare from FPGA pin Y13 | |
|
SDO_LMK |
C27 |
Spare from FPGA pin AE13 | |
|
SCL |
C30 |
Spare USB2.0 I/F | |
|
SDA |
C31 |
Spare USB2.0 I/F | |
|
NCOA0 |
J18 |
Spare from FPGA pin AF15 | |
|
NCOA1 |
J19 |
Spare from FPGA pin Y16 | |
|
NCOB0 |
J21 |
Spare from FPGA pin G22 | |
|
NCOB1 |
J22 |
Spare from FPGA pin F22 | |
|
CDBUS2-5 |
G27, G28, G33, G34 |
Spare USB2.0 I/O's |
|
|
DDBUS0-3 |
G21, G22, G36, G37 |
Spare USB2.0 I/O's | |