The TSW14J58EVM includes one industry-standard JTAG connector, P2, that connects to the JTAG port of the FPGA. The USB 2.0 interface on the TSW14J58EVM allows for the FPGA to be programmed from the JTAG connector or the USB 2.0 interface. The USB 2.0 interface allows the FPGA to be programmed using the HSDC Pro software GUI. Every time the TSW14J58EVM is powered-down, the FPGA configuration is removed. The user must program the FPGA through the GUI after every time the board is powered-up. The FPGA can also be configured using the two on-board flash devices, U3 and U6.

FLASH DEVICES The TSW14J58EVM includes two serial flash programming EEPROMS that can load FPGA firmware. From the factory, U3 is loaded with a file called JESD204B_1p4.mcs which will configure the FPGA to operate in JESD204B mode. U6 is loaded with a file called JESD204C_1p4.mcs which will configure the FPGA to operate in JESD204C mode. Jumper J35 determines which EEPROM will configure the FPGA when switch SW4 is pressed. After power up, pressing SW4 will load the FPGA with the factory pre-programmed flash device U3 if J35 has a shunt between pins 1-2 and U6 if the shunt is between pins 2-3 or removed.

Program the Memory Device

To program U3 and U6 with new files, use the following steps:

1. Connect the TSW14J58 Capture card to the PC through a JTAG Xilinx Programmer cable. This will be the JTAG connect P2.
2. Open the Vivado Installation:
   • Double click “Open Hardware Manager”.
3. In the Hardware Manager, left click on “Open target” and select “Auto Connect”.
4. This will list all the FPGAs connected to the PC through JTAG Programmer cables.
5. Right click on “xcku5p_0” -> click on “Add Configuration Memory Device”.
   Figure 3-1 Add Configuration Memory Device
6. In the pop-up window, search for the “mt25qu256-spi-x1_x2_x4” component. Click the OK button.
7. Right click on device “mt25qu256-spi-x1_x2_x4”, and click on “Program Configuration Memory Device” (see Figure 3-2).
   Figure 3-2 Programming Memory Device
8. With J35 = 1–2, open up the new “xx.mcs” file to be loaded, and check the following setup in the programming. Click the OK button when completed. Figure 3-3 illustrates the configuration file to be loaded.
   Figure 3-3 Config file
9. Press SW4 to reload the EEPROM
10. Press SW3 to reset FPGA
11. With J35 = 2–3, open up the new “yy.mcs”file to be loaded and check the following setup in the programming. Click the OK button when completed.