3 Fixed-frequency DCS-Control topology overview

Figure 2 shows a basic block diagram of the fixed-frequency DCS-Control topology, as implemented in the 15A TPS62873 buck converter. The addition of an oscillator enables the direct setting of the switching frequency (f_SW) in the same way as voltage- or current-mode control. Having an oscillator input into the control loop also provides the ability to synchronize the switching frequency to an applied clock signal.

Fixed-frequency DCS-Control, usually used in higher-current devices, uses differential remote sensing. The device regulates the voltage between the VOSNS and GOSNS pins, which are routed across the printed circuit board (PCB) to sense the output voltage directly at the load. Sensing at the load overcomes and compensates for not only the DC voltage drops across the PCB planes and traces, but also the delays that come from inductance between the device and the load. Both of these characteristics are important for maintaining very tight regulation across the load range and during load transients.

The differential remote-sensing signals are fed into the transconductance amplifier (g_m), which compares their difference against the output voltage setpoint. (For simplicity, Figure 2 shows this setpoint as a voltage source in series with the GOSNS signal.) The COMP pin gives the output of this amplifier, which is compensated with a Type II (one pole, one zero) network to ground.

This external compensation allows you to optimize the control loop to any system need – from systems with strong load transients with large output capacitance, all the way down to systems with small or no load transients with very little output capacitance and small size. Unlike DCS-Control, the fast feedback path goes through this amplifier – not immediately to the comparator – where compensation component selection can increase (or decrease) the gain. If you need a stronger transient response, you increase the gain and add more output capacitance. If no strong transients are present in the application, you decrease the gain and use a minimal amount of output capacitance in order to achieve the smallest size.

The ability to adjust the transient response to the application needs enables tighter regulation under harsher transients than what is possible with the previous DCS-Control topology, and meets the requirements of demanding processor cores such as TI’s Jacinto™ J7 and MobileEye’s EyeQ6 [3-4]. Figure 3 shows a stack of three TPS62876-Q1 buck converters delivering a 46A load transient, while maintaining the output voltage within ±2% of the 0.875V setpoint.

A hysteretic comparator compares the COMP pin output and a replica of the inductor current, created by the τ_aux components, with slope compensation added to prevent subharmonic oscillations. The comparator’s output drives the Set-Reset (SR) latch circuitry, along with the clock, which controls the gate drivers and device operation. The oscillator controls the switching to occur exactly at the switching frequency.

The Set-Reset latch is a simplified representation of the detailed operation of the control block and is implemented to maintain the fast, hysteretic nature of DCS-Control and thus enable an immediate response to load transients. For example, during a load-dump transient (where the output voltage rises), the output of the hysteretic comparator has priority over the clock signal. The converter extends the off-time of the high-side MOSFET as needed to bring the output voltage back down with minimum overshoot. This is inherently improved behavior compared to textbook peak current-mode control, which switches at every clock cycle, continuing to add energy to the output, even while it is too high. By reducing the output-voltage overshoot, the converter significantly reduces the output capacitance, which is a key influence on the cost and size of the power supply.