SLYT862 March 2025 LM5066I , TPS25984B
Figure 8 shows the sequence of events that could happen internal to the IC when taking the OUT pin below ground. The parasitic PN junction diode starts conducting, which injects free electrons into the substrate. These free electrons interfere with other control units that could reset the IC or cause a latch-up event. A large current conduction through the parasitic PN junction diode could cause EOS and lead to EIPD.
It is possible to prevent these issues by either reducing the peak negative voltage at the OUT pin or by limiting the current through the OUT pin. Adding an output capacitor close to the OUT pin will absorb some of the energy from the negative voltage spike and control the slew rate to limit the peak negative voltage. Adding a low-forward-voltage Schottky diode at the OUT pin provides an alternate path for current and limits the current through the IC.
Effective clamping requires a combination of capacitors and Schottky diodes. While a higher-output capacitor is helpful, use these guidelines when selecting a Schottky diode:
We used two SBR10U45SP5 [6] diodes from Diodes Incorporated in parallel in this application.
Figure 8 Graphical illustration showing
the consequences inside the IC when taking the output below ground.Figure 9 shows the output clamping performance with and without Schottky diodes in the TPS25984B solution.
Figure 9 Transient protection at the
output of the eFuse.When dealing with high-current hot-swap solutions, secondary protection (shown in Figure 10) can minimize the Schottky diode requirement at the output. As you can see, D1 will absorb most of the energy from the negative voltage transient. Adding a small-value resistor (R1) such as 47Ω and a diode (D2) such as an SS13 will significantly limit the remaining energy.
Figure 10 Secondary protection in
high-current hot-swap solutions.