SNAA333 April   2020 CDCE6214-Q1

 

  1.   eAVB Media Clock Synchronization Using CDCE6214-Q1 Clock Generator
    1.     Trademarks
    2. 1 Introduction
    3. 2 AVB Protocols and Network Structure
    4. 3 AVB End Station Architecture
    5. 4 Talker, Listener, Presentation Time, and Media Clock Synchronization
      1. 4.1 Talker and Presentation Time
      2. 4.2 Listener and Media Clock Synchronization
    6. 5 Reference CDCE6214-Q1 Schematic and Programming Guide
    7. 6 Summary
    8. 7 References

5 Reference CDCE6214-Q1 Schematic and Programming Guide

A simplified CDCE6214-Q1 schematic is shown below:

06-IC-schematic.gifFigure 6. AVB Clocking Schematic

CDCE6214-Q1 has integrated crystal driver circuit, so only a simple crystal resonator is needed at the input. The XTAL (crystal) selection and programming guide can be found at CDCE6214-Q1 Crystal-Based Oscillator Design. The media clock can be generated out of OUT1_P. OUT0 bypasses PLL and produces buffered output from the crystal input. This 25-MHz output can be used to clock Ethernet. The frequency increment and decrement commands coming from media clock recovery module is fed back to the CDCE6214-Q1 device through the I2C (it can also be fed through the GPIO pin control)

The frequency increment and decrement step size can be set by register R43[15:0] FREQ_INC_DEC_DELTA. The VCO (Voltage Controlled Oscillator) frequency step size is PFD_FREQ / PLL_DEN × FREQ_INC_DEC_DELTA, where PFD_FREQ is phase frequency detector frequency and PLL_DEN is the denominator of PLL fractional divider. The output frequency step size is VCO frequency step size divided by output divider. An example calculation can be found in Table 1. Alternatively, the calculation can be done in TicsPro.

Table 1. Computing Divider Settings in DCO Mode

PARAMETERS VALUE (EXAMPLE) DESCRIPTION
Input PFD Frequency (FPFD) 25 MHz Set according to FPFD.
Expected VCO Frequency (FVCO) 2457.6 MHz FVCO is set within the operating VCO range of 2335 MHz - 2625 MHz. FVCO is selected such that PSA/PSB/Output Divider is Integer.
Expected Output Frequency (FOUT) 24.576 MHz PSA = 4, IOD = 25. FVCO = PSA × IOD × FOUT.
Expected step size (in ppm) (Fstep) 0.1 Every rising edge of FREQ_INC/FREQ_DEC would change the output by this step size.
N-divider Value (N) 98 INT(FVCO/FPFD)
Minimum Numerator value to meet 0ppb accuracy (Num) 76 These values are computed to meet accuracy requirement at output. Should be less than 224.
Minimum Denominator to meet 0ppb accuracy (Den) 250
Minimum Denominator value to meet ppm step size (FDEN,min) 101725.26 1/(Fstep × 1e6) / (FVCO/FPFD)
Final Denominator value (FDEN,final) 500000 FDEN,final should be greater than FDEN,min and less than 224. FDEN,final and FNUM,final should be integer multiple of Den and Num respectively. FDEN,final/Den = FNUM,final/Num
Final Numerator value (FNUM,final) 152000
Increment/ Decrement step size 5 This value should be less than 216-1. FDEN,final should be closest integer multiple of FDEN,min.

Once the step size is set, DCO mode is enabled (R3[3] FREQ_INC_DEC_EN = 1) and DCO register control is enabled (R3[4] FREQ_INC_DEC_REG_MODE = 1), the frequency can be incremented or decremented by toggling R3[5] FREQ_INC_REG and R3[6] FREQ_DEC_REG