Product details

Function Clock generator Number of outputs 4 Output frequency (Max) (MHz) 328.125 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type XTAL, LVCMOS, Differential Output type LVCMOS, LVDS, HCSL Operating temperature range (C) -40 to 105 TI functional safety category Functional Safety-Capable Features Pin programmable, Integrated EEPROM, Serial interface Rating Automotive
Function Clock generator Number of outputs 4 Output frequency (Max) (MHz) 328.125 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type XTAL, LVCMOS, Differential Output type LVCMOS, LVDS, HCSL Operating temperature range (C) -40 to 105 TI functional safety category Functional Safety-Capable Features Pin programmable, Integrated EEPROM, Serial interface Rating Automotive
VQFN (RGE) 24 16 mm² 4 x 4
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 2: –40°C to +105°C
  • Functional Safety-Capable
    • Documentation available to aid functional safety system design
  • Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, Fout > 100 MHz) as:
    • Integer mode:
      • Differential output: 350 fs typical, 600 fs maximum
      • LVCMOS output: 1.05 ps typical, 1.5 ps maximum
    • Fractional mode:
      • Differential output: 1.7 ps typical, 2.1 ps maximum
      • LVCMOS output: 2.0 ps typical, 4.0 ps maximum
  • Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC
  • 2.335-GHz to 2.625-GHz internal VCO
  • Typical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.
  • Universal clock input, two reference inputs for redundancy
    • Differential AC-coupled or LVCMOS: 10 MHz to 200 MHz
    • Crystal: 10 MHz to 50 MHz
  • Flexible output clock distribution
    • 4 channel dividers: Up to 5 unique output frequencies from 24 kHz to 328.125 MHz
    • Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
    • Glitchless output divider switching and output channel synchronization
    • Individual output enable through GPIO and register
  • Frequency margining options
    • DCO mode: frequency increment/decrement with 10ppb or less step-size
  • Fully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHz
  • Single or mixed supply for level translation: 1.8 V/2.5 V/3.3 V
  • Configurable GPIOs and flexible configuration options
    • I2C-compatible interface: up to 400 kHz
    • Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
  • Supports 100-Ω systems
  • Low electromagnetic emissions
  • Small footprint: 24-pin VQFN (4 mm × 4 mm)
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 2: –40°C to +105°C
  • Functional Safety-Capable
    • Documentation available to aid functional safety system design
  • Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, Fout > 100 MHz) as:
    • Integer mode:
      • Differential output: 350 fs typical, 600 fs maximum
      • LVCMOS output: 1.05 ps typical, 1.5 ps maximum
    • Fractional mode:
      • Differential output: 1.7 ps typical, 2.1 ps maximum
      • LVCMOS output: 2.0 ps typical, 4.0 ps maximum
  • Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC
  • 2.335-GHz to 2.625-GHz internal VCO
  • Typical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.
  • Universal clock input, two reference inputs for redundancy
    • Differential AC-coupled or LVCMOS: 10 MHz to 200 MHz
    • Crystal: 10 MHz to 50 MHz
  • Flexible output clock distribution
    • 4 channel dividers: Up to 5 unique output frequencies from 24 kHz to 328.125 MHz
    • Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
    • Glitchless output divider switching and output channel synchronization
    • Individual output enable through GPIO and register
  • Frequency margining options
    • DCO mode: frequency increment/decrement with 10ppb or less step-size
  • Fully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHz
  • Single or mixed supply for level translation: 1.8 V/2.5 V/3.3 V
  • Configurable GPIOs and flexible configuration options
    • I2C-compatible interface: up to 400 kHz
    • Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
  • Supports 100-Ω systems
  • Low electromagnetic emissions
  • Small footprint: 24-pin VQFN (4 mm × 4 mm)

The CDCE6214-Q1 is a four-channel, ultra-low power, medium grade jitter, clock generator for automotive application that can generate five independent clock outputs selectable between various modes of drivers. The input source could be a single-ended or differential input clock source, or a crystal. The CDCE6214-Q1 features a frac-N PLL to synthesize unrelated base frequency from any input frequency. The CDCE6214-Q1 can be configured through the I2C interface. In the absence of the serial interface, the GPIO pins can be used in Pin Mode to configure the product into distinctive configurations.

The CDCE6214-Q1 is a four-channel, ultra-low power, medium grade jitter, clock generator for automotive application that can generate five independent clock outputs selectable between various modes of drivers. The input source could be a single-ended or differential input clock source, or a crystal. The CDCE6214-Q1 features a frac-N PLL to synthesize unrelated base frequency from any input frequency. The CDCE6214-Q1 can be configured through the I2C interface. In the absence of the serial interface, the GPIO pins can be used in Pin Mode to configure the product into distinctive configurations.

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Technical documentation

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Type Title Date
* Data sheet CDCE6214-Q1 Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM datasheet (Rev. B) 14 Oct 2021
Functional safety information CDCE6214-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA 15 Apr 2021
Technical article Optimizing eAVB for automotive applications using clock generators 08 May 2020
Certificate CDCE6214-Q1EVM Declaration of Conformity (DoC) 28 Apr 2020
Application note Frequency Margining and eAVB System Design With CDCE6214-Q1 02 Apr 2020
Application note CDCE6214-Q1 Crystal-Based Oscillator Design 09 Dec 2019
User guide CDCE6214-Q1 EVM User's Guide (Rev. A) 27 Nov 2019
User guide CDCE6214-Q1 Registers (Rev. B) 27 Nov 2019
Technical article How to select an optimal clocking solution for your FPGA-based design 09 Dec 2015
Technical article Clocking sampled systems to minimize jitter 31 Jul 2014
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications 28 Mar 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

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Evaluation board

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Application software & framework

TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software

The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
Simulation model

CDCE6214-Q1 IBIS Model

SNAM233.ZIP (251 KB) - IBIS Model
Simulation tool

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Design tool

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VQFN (RGE) 24 View options

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