SNAA366 October   2022 LMX1204

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Basic Clock Distribution System
    2. 1.2 Pre-multiplier Stage
  4. 2Low-Frequency Reference
    1. 2.1 Pre-multiplier Stage
    2. 2.2 LMX1204 Multiplier Stage
    3. 2.3 LMX1204 Multiplier vs RF Synthesizer
  5. 3Real-World Application With AFE7950 RF Sampling Transceiver
    1. 3.1 AFE7950 Clocking Measurement Setup
    2. 3.2 AFE7950 Clocking Measurement Results
  6. 4Conclusion

2.2 LMX1204 Multiplier Stage

The LMX1204 device multiplies the 1474.56 MHz by 4 × to achieve the final output sampling frequency of 5898.24 MHz. Figure 2-4 shows the performance of the sample clock phase noise compared to the test equipment sources.

GUID-20220906-SS0I-DX12-D0KX-CHBSBXLRV2SZ-low.png Figure 2-4 Phase-Noise Comparison of 5898.24-MHz Signal

The multiplier circuitry does introduce some phase-noise degradation, particularly evident at the higher frequency offsets beginning at around 1-MHz offset. The performance is still good and still surpasses the Agilent PSG for offsets below the 300-kHz offset. With the multiplier (and the phase-noise contribution of the multiplier) the absolute performance of the source becomes diminished; the performance using the LMX1204 multiplier with the SMA100B as the source versus the pre-multiplier as the source is nearly the same. Table 2-3 reports the integrated jitter performance.

Table 2-3 Integrated Jitter at 5898.24 MHz
Frequency Source RMS Jitter
5898.24 MHz R&S SMA100B 5.4 fs
R&S SMA100B - LMX1204 - 4x 26.4 fs
Wenzel Osc - 3x - LMX1204 - 4x 33.6 fs
Agilent PSG 19.4 fs