Product details

Integrated VCO No Output frequency (Min) (MHz) 300 Output frequency (Max) (MHz) 12800 Current consumption (mA) 405 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -161
Integrated VCO No Output frequency (Min) (MHz) 300 Output frequency (Max) (MHz) 12800 Current consumption (mA) 405 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -161
VQFN (RHA) 40
  • 300-MHz to 12.8-GHz output frequency
  • Noise floor of –160 dBc/Hz at 6-GHz output
  • Under 30-fs additive jitter (DC to fCLK integration range)
  • 4 high-frequency clocks with corresponding SYSREF outputs
    • Shared divide by 1 (Bypass), 2, 3, 4, 5, 6, 7, and 8
    • Shared programmable multiplier x2, x3, and x4
  • LOGICLK output with corresponding SYSREF output
    • On separate divide bank
    • 1, 2, 4 pre-divider
    • 1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • Synchronized SYSREF clock outputs
    • 508 delay step adjustments of less than 2.5 ps each at 12.8 GHz
    • Generator and repeater modes
    • Windowing feature for SYSREFREQ pins to optimize timing
  • SYNC feature to all divides and multiple devices
  • 2.5-V operating voltage
  • –40ºC to +85ºC operating temperature
  • 300-MHz to 12.8-GHz output frequency
  • Noise floor of –160 dBc/Hz at 6-GHz output
  • Under 30-fs additive jitter (DC to fCLK integration range)
  • 4 high-frequency clocks with corresponding SYSREF outputs
    • Shared divide by 1 (Bypass), 2, 3, 4, 5, 6, 7, and 8
    • Shared programmable multiplier x2, x3, and x4
  • LOGICLK output with corresponding SYSREF output
    • On separate divide bank
    • 1, 2, 4 pre-divider
    • 1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • Synchronized SYSREF clock outputs
    • 508 delay step adjustments of less than 2.5 ps each at 12.8 GHz
    • Generator and repeater modes
    • Windowing feature for SYSREFREQ pins to optimize timing
  • SYNC feature to all divides and multiple devices
  • 2.5-V operating voltage
  • –40ºC to +85ºC operating temperature

The high frequency capability and extremely low jitter of this device, makes a great solution to clock precision, high-frequency data converters without degradation to the signal-to-noise ratio. Each of the 4 high frequency clock outputs and additional LOGICLK output with larger divider range, is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. For data converter clocking applications, it is critical to have the jitter of the clock be less than the aperture jitter of the data converter. In applications where more than 4 data converters need to be clocked, a variety of cascading architectures can be developed using multiple devices to distribute all the high frequency clocks and SYSREF signals required. With 30 fs of additive jitter and a noise floor of -160 dBc/Hz, this device combined with an ultra-low noise reference clock source is an exemplary solution for clocking data converters, especially when sampling above 3 GHz.

The high frequency capability and extremely low jitter of this device, makes a great solution to clock precision, high-frequency data converters without degradation to the signal-to-noise ratio. Each of the 4 high frequency clock outputs and additional LOGICLK output with larger divider range, is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. For data converter clocking applications, it is critical to have the jitter of the clock be less than the aperture jitter of the data converter. In applications where more than 4 data converters need to be clocked, a variety of cascading architectures can be developed using multiple devices to distribute all the high frequency clocks and SYSREF signals required. With 30 fs of additive jitter and a noise floor of -160 dBc/Hz, this device combined with an ultra-low noise reference clock source is an exemplary solution for clocking data converters, especially when sampling above 3 GHz.

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Technical documentation

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Type Title Date
* Data sheet LMX1204 Low-Noise, High-Frequency JESD Buffer/Multiplier/Divider datasheet 27 Jul 2021
User guide LMX1204 Register Map 23 Aug 2021
User guide LMX1204EVM User's Guide 15 Jul 2021

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMX1204EVM — Evaluation module for LMX1204, an RF buffer, multiplier, and divider with JESD204B/C SYSREF support

The LMX1204 evaluation module (EVM) is designed to evaluate the performance of the LMX1204, which is a four-output, ultra-low additive-jitter RF buffer, divider, and multiplier. This EVM can buffer RF clocking inputs up to 12.8 GHz, multiply x2, x3, or x4 in the output range of 3.2 GHz to 6.4 GHz (...)
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Application software & framework

PLLATINUMSIM-SW — Texas Instruments PLLatinum Simulator Tool

The PLLATINUMSIM-SW simulator tool lets you create detailed designs and simulations of our PLLATINUM™ integrated circuits which include the LMX series of PLLs and synthesizers.
Application software & framework

TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software

The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
Support software

TICS Pro Software v1.7.2 (Rev. AL)

SNAC072AL.ZIP (61999 KB)
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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VQFN (RHA) 40 View options

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