SNAA434 March   2025 LMX2820

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Creating Multiple Copies of the Input Signal
    1. 2.1 Skew and Slew Rate Considerations
    2. 2.2 Buffers vs. Resistive Splitters
    3. 2.3 Phase Noise Considerations With Buffers
  6. 3Considerations with Combining Outputs
    1. 3.1 Isolation Between Sources
    2. 3.2 Single-Ended vs. Differential Outputs
    3. 3.3 Losses Due to Combining
  7. 4Resistive Method for Combining Multiple Signals
    1. 4.1 General Case Where Source Output Impedance can be Different Than Load Impedance
    2. 4.2 Special Case Where Source and Load Impedance are the Same
    3. 4.3 Increasing R1 to Improve Isolation
  8. 5Impedance Matching With Reactive Circuit
  9. 6Loss Due to Phase Error
  10. 7Phase Noise Improvement by Combining Multiple Signals
    1. 7.1 Theoretical Improvement for Multiple Signals Designed for in Phase
    2. 7.2 Combining Multiple Signals With a Phase Error
  11. 8Summary
  12. 9References
  13.   A Appendix: Calculations for Resistive Matching Network
  14.   B Appendix: Calculations for Reactive Matching Network
  15.   C Appendix: Calculation of Loss Due to Phase Error

2.3 Phase Noise Considerations With Buffers

Assuming a noiseless input source, we want the buffer noise to be lower than that of the PLL. For the PLL, this noise gets reduced when multiple synthesizers are combined together. For the buffer, only the output state noise gets reduced by the combining, but the input stage goes straight to the output. Table 2-1 shows an analysis with just one source to show the challenge of finding a buffer with adequate phase noise.

Table 2-1 Buffer Phase Noise Comparison
Frequency LMX2820 PLL LMK12C104 Buffer LMK12D104 Buffer LMX1204 Buffer
Skew

Prop. Delay Variation:

60ps (typ)

Output-Output Skew:

50ps (max)

Output-Output Skew:

20ps (max)

Output-Output Skew:

1ps (typ)

15ps (max)
10MHz -166 -170 -163.0 x
50MHz -159 -170 -162.7 x
100MHz -156 -170 -161.6 x
250MHz -152 -168 -160.2 x
500MHz -146 x -159.1 -161
1GHz -143 x -158.1 -161

The PLL noise floor can be calculated by taking the PLL figure of merit and adding 10×log(fPD). fPD is the phase detector frequency, which is equal to the input frequency, provided the phase detector goes that high. If not, then this is degraded. For Table 2-1, a PLL figure of merit of -236dBc/Hz was assumed and the maximum phase detector frequency is 400MHz, so this is why the phase noise degrades at a faster rate after 250MHz. There is also the 1/f noise of the PLL that needs to be compared to that of the buffer. Keep in mind that this is for a single synthesizer, combining the synthesizers makes the noise requirement more stringent for the buffer.