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LMX2820

ACTIVE

22.6-GHz wideband RF synthesizer with phase synchronization, JESD and <5-µs frequency calibration

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Data sheet

LMX2820

ACTIVE
Data sheet Order now

Product details

Frequency (max) (MHz) 22600 Frequency (min) (MHz) 45 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -134 Features Integer-boundary spurs (IBS) removal, Integrated VCO, JESD204B SYSREF, Multi-device sync, Phase adjustment, Ultra-fast VCO Calibration, Wideband Current consumption (mA) 500 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
Frequency (max) (MHz) 22600 Frequency (min) (MHz) 45 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -134 Features Integer-boundary spurs (IBS) removal, Integrated VCO, JESD204B SYSREF, Multi-device sync, Phase adjustment, Ultra-fast VCO Calibration, Wideband Current consumption (mA) 500 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
VQFNP (RTC) 48 49 mm² 7 x 7
  • Output frequency: 45 MHz to 22.6 GHz
  • 36-fs rms jitter (12 kHz – 95 MHz) at 6 GHz
  • High-performance PLL
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –134 dBc/Hz
    • -95 dBc Integer Mode Spurs (fPD=100 MHz)
    • High phase detector frequency
      • 400-MHz integer mode
      • 300-MHz fractional mode
    • Programmable input multiplier
    • Direct PFD input for offset mixing support allowing PLL N divider to be one for ultra-low jitter
  • 2.5-µs fast VCO calibration time
  • Mute pin with 200-ns mute/unmute time
  • –45-dBc VCO leakage with doubler enabled
  • Support for external VCO up to 22.6-GHz
  • Synchronization of output phase across multiple devices
  • Two differential RF outputs and one differential SYSREF output for JESD204B support
  • Output frequency: 45 MHz to 22.6 GHz
  • 36-fs rms jitter (12 kHz – 95 MHz) at 6 GHz
  • High-performance PLL
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –134 dBc/Hz
    • -95 dBc Integer Mode Spurs (fPD=100 MHz)
    • High phase detector frequency
      • 400-MHz integer mode
      • 300-MHz fractional mode
    • Programmable input multiplier
    • Direct PFD input for offset mixing support allowing PLL N divider to be one for ultra-low jitter
  • 2.5-µs fast VCO calibration time
  • Mute pin with 200-ns mute/unmute time
  • –45-dBc VCO leakage with doubler enabled
  • Support for external VCO up to 22.6-GHz
  • Synchronization of output phase across multiple devices
  • Two differential RF outputs and one differential SYSREF output for JESD204B support

The LMX2820 is a high-performance, wideband synthesizer that can generate any frequency in the range of 45 MHz to 22.6 GHz. The high performance PLL with figure of merit of –236 dBc/Hz and high phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2820 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. The fast calibration algorithm greatly reduces the VCO calibration time, enabling systems requiring fast frequency hopping. The LMX2820 can generate or repeat SYSREF that is compliant to the JESD204B standard, allowing for its use as a low-noise clock source for high-speed data converters. This synthesizer can also be used with an external VCO. A direct PFD input pin is provided to support offset mixing for low spurious transmission.

The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for onboard low-noise LDOs.

The LMX2820 is a high-performance, wideband synthesizer that can generate any frequency in the range of 45 MHz to 22.6 GHz. The high performance PLL with figure of merit of –236 dBc/Hz and high phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2820 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. The fast calibration algorithm greatly reduces the VCO calibration time, enabling systems requiring fast frequency hopping. The LMX2820 can generate or repeat SYSREF that is compliant to the JESD204B standard, allowing for its use as a low-noise clock source for high-speed data converters. This synthesizer can also be used with an external VCO. A direct PFD input pin is provided to support offset mixing for low spurious transmission.

The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for onboard low-noise LDOs.
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Technical documentation

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* Data sheet LMX2820 22.6-GHz Wideband PLLatinum RF Synthesizer With Phase Synchronization and JESD204B Support datasheet (Rev. C) PDF | HTML 04 Feb 2021
Application note Using Instant Calibration With the LMX2820 PDF | HTML 14 Jun 2025
Application note Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML 11 Apr 2025
Application note Combining More than Two Signals for Better Noise PDF | HTML 24 Mar 2025
Application brief Compilation of RF Synthesizer Resources PDF | HTML 22 Oct 2024
Application note Sine to Square Wave Conversion Using Clock Buffers PDF | HTML 03 Sep 2024
Application brief Common Mistakes While Designing With Rf Clock Synthesizers and How To Mitigate the Same PDF | HTML 08 Aug 2024
Circuit design MASH_SEED Optimization and Impact on Spurs (LMX2820) PDF | HTML 08 Aug 2024
Application brief High-Frequency Clock (> 20GHz) Skew Variation Between Two RF Synthesizers Across Temperature PDF | HTML 26 Apr 2024
Application brief High-Frequency Delay Adjustments Between Two RF Synthesizers PDF | HTML 26 Apr 2024
Application brief LMX2820 with Internal Doubler versus LMX2594 PDF | HTML 16 Jan 2024
Application note LMX2820 RF Synthesizer Phase Noise Improvement With Alternative Topologies (Rev. A) PDF | HTML 22 May 2023
Application note External Doubler Extends LMX2820 Operation to 44 GHz PDF | HTML 31 Mar 2023
User guide How to Phase Synchronize Multiple LMX2820 Devices PDF | HTML 19 Dec 2022
Application note High Isolation, Fast Frequency Switching With LMX2820 in Ping-Pong Architecture PDF | HTML 20 Sep 2022
Application note Combining Two LMX2820 Synthesizer Outputs for Improved Phase Noise (Rev. A) PDF | HTML 03 Mar 2022
User guide LMX2820 Register Map (Rev. A) 09 Dec 2020
Application note Impact of PLL Jitter to GSPS ADC's SNR and Performance Optimization 11 Nov 2020
Application note Dramatically Improve Your Lock Time with VCO Instant Calibration PDF | HTML 17 Sep 2020
Certificate LMX2820EVM EU Declaration of Conformity (DoC) 09 Jun 2020

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMX2820EVM — LMX2820 22.6-GHz wideband RF synthesizer evaluation module

This evaluation module is for the LMX2820, which is a 22.6-GHz wideband RF synthesizser. This synthesizer supports JESD204B compliant SYSREF signal buffering and generation. The LMX2820 allows designers to synchronize the output of multiple instances of the device.
User guide: PDF | HTML
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Support software

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

Supported products & hardware

Supported products & hardware
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Simulation model

LMX2820 IBIS model

SNAM245.ZIP (45 KB) - IBIS Model
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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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Design tool

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware
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Reference designs

TIDA-010230 — Multi-channel RF transceiver, low-noise clocking reference design for radar and EW applications

In modern radar and electronic warfare (EW) systems, active electronically-scanned array (AESA) antenna systems are often used with high speed multi-channel RF transceivers. These systems require very low noise clocking capable of precise channel-to-channel skew adjustment to achieve the optimal (...)
Design guide: PDF
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VQFNP (RTC) 48 Ultra Librarian
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