SNAU264 July   2021 CDCDB800

 

  1. 1 Trademarks
  2. 2 General Description
    1. 2.1 Features
  3. 3 Quick Setup
    1. 3.1 Setup Procedure
  4. 4 Signal Path and Control Switches
  5. 5 Power Supplies
  6. 6 Clock Inputs
    1. 6.1 Configuring Board for CDCDB803
  7. 7 Clock Outputs
  8. 8 Using SMBus
    1. 8.1 CDCDB803 SMBus Address
  9. 9 Schematics
  10. 10Bill of Materials

6 Clock Inputs

The SMA inputs labeled CLKin_P (J1) & CLKin_N (J2) can be configured to receive a differential clock or single-ended clock. The best performance is achieved with an AC differential input clock—the default configuration. Input transmission lines use 50-Ω single-ended impedance, 100-Ω differential impedance.

CLKin paths include footprint options to provide the user with flexibility in configuring the termination, biasing, and coupling for the device inputs. Please take care to follow the Vin electrical parameters shown in the datasheet SNAS818.