Top

Product details

Parameters

Function Differential Additive RMS jitter (Typ) (fs) 38 Output frequency (Max) (MHz) 250 Number of outputs 8 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features 1:8 fanout, PCIe Gen 1-5 compliant, DB800ZL compliant, SMBus control, OE# control, Individual output enable control Operating temperature range (C) -40 to 105 Rating Catalog Output type LP-HCSL Input type LP-HCSL open-in-new Find other Clock buffers

Package | Pins | Size

VQFN (RSL) 48 36 mm² 6 x 6 open-in-new Find other Clock buffers

Features

  • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations
  • 8 hardware output enable (OE#) controls
  • Additive phase jitter after PCIE Gen5 filter: < 25 fs, RMS (maximum)
  • Additive phase jitter after DB2000Q filter: < 38 fs, RMS (maximum)
  • Supports PCIe Gen 4 and Gen 5 Common Clock (CC) and Individual Reference (IR) architectures
    • Spread spectrum-compatible
  • Output-to-output skew: < 50 ps
  • Input-to-output delay: < 3 ns
  • Fail-safe input

  • Programmable output slew rate control

  • 3.3-V core and IO supply voltages
  • Hardware-controlled low power mode (PD#)
  • Current consumption: 72 mA maximum
  • 6-mm × 6-mm, 48-pin VQFN package
open-in-new Find other Clock buffers

Description

The CDCDB800 is a 8-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-5, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus interface and eight output enable pins allow the configuration and control of all eight outputs individually. The CDCDB800 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. It also meets or exceeds the parameters in the DB2000Q specification. The CDCDB800 is packaged in a 6-mm × 6-mm, 48-pin VQFN package.

open-in-new Find other Clock buffers
Download
Similar products you might be interested in
open-in-new Compare products
Same functionality with different pin-out to the compared device.
CDCDB2000 ACTIVE DB2000QL compliant 20-output clock buffer for PCIe® Gen 1 to Gen 5 20-output, DB2000QL compliant version
NEW CDCDB803 ACTIVE 8-output clock buffer for PCIe® Gen 1 to Gen 5 with selectable SMBus addresses Slightly varied pinout to the CDCDB800

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* Data sheet CDCDB800 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5 datasheet Jul. 16, 2021
User guide CDCDB800/803 Ultra-Low Additive Jitter, 8-Output PCIe Gen1 to Gen5 Clock Buffer Jul. 16, 2021

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
225
Description
CDCDB800 evaluation module is an 8-output LP-HCSL, DB800ZL compliant, clock buffer capable of distributing the reference clock for PCIe® Gen 1 to Gen 5 application, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus interface and eight outputs enable pins to allow the (...)
Features
  • Easy to use evaluation board to fanout up to 8 LP-HCSL clocks
  • Output enable pin configurable through DIP switch
  • Board powered from a single 3.3 V supply

Software development

SUPPORT SOFTWARE Download
SNAC072AK.ZIP (62249 KB)

Design tools & simulation

SIMULATION MODEL Download
SNAM247.ZIP (30 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
VQFN (RSL) 48 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos