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CDCDB800

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8-output clock buffer for PCIe® Gen 1 to Gen 6

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Data sheet

CDCDB800

ACTIVE
Data sheet Order now

Product details

Function Clock buffer, Differential Additive RMS jitter (typ) (fs) 38 Output frequency (max) (MHz) 250 Number of outputs 8 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features 1:8 fanout, DB800ZL compliant, Individual output enable control, OE# control, PCIe Gen 1-5 compliant, SMBus control Operating temperature range (°C) -40 to 105 Rating Catalog Output type LP-HCSL Input type LP-HCSL
Function Clock buffer, Differential Additive RMS jitter (typ) (fs) 38 Output frequency (max) (MHz) 250 Number of outputs 8 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features 1:8 fanout, DB800ZL compliant, Individual output enable control, OE# control, PCIe Gen 1-5 compliant, SMBus control Operating temperature range (°C) -40 to 105 Rating Catalog Output type LP-HCSL Input type LP-HCSL
VQFN (RSL) 48 36 mm² 6 x 6
  • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations
  • 8 hardware output enable (OE#) controls
  • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)
  • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)
  • Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)
  • Supports Common Clock (CC) and Individual Reference (IR) architectures
    • Spread spectrum-compatible
  • Output-to-output skew: < 50 ps
  • Input-to-output delay: < 3 ns

  • Fail-safe input

  • Programmable output slew rate control

  • 3.3-V core and IO supply voltages
  • Hardware-controlled low power mode (PD#)
  • Current consumption: 72 mA maximum
  • 6-mm × 6-mm, 48-pin VQFN package
  • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations
  • 8 hardware output enable (OE#) controls
  • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)
  • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)
  • Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)
  • Supports Common Clock (CC) and Individual Reference (IR) architectures
    • Spread spectrum-compatible
  • Output-to-output skew: < 50 ps
  • Input-to-output delay: < 3 ns

  • Fail-safe input

  • Programmable output slew rate control

  • 3.3-V core and IO supply voltages
  • Hardware-controlled low power mode (PD#)
  • Current consumption: 72 mA maximum
  • 6-mm × 6-mm, 48-pin VQFN package

The CDCDB800 is a 8-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus interface and eight output enable pins allow the configuration and control of all eight outputs individually. The CDCDB800 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. It also meets or exceeds the parameters in the DB2000Q specification. The CDCDB800 is packaged in a 6-mm × 6-mm, 48-pin VQFN package.

The CDCDB800 is a 8-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus interface and eight output enable pins allow the configuration and control of all eight outputs individually. The CDCDB800 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. It also meets or exceeds the parameters in the DB2000Q specification. The CDCDB800 is packaged in a 6-mm × 6-mm, 48-pin VQFN package.
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Technical documentation

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Type Title Date
* Data sheet CDCDB800 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6 datasheet (Rev. B) PDF | HTML 23 May 2022
EVM User's guide CDCDB800/803 Ultra-Low Additive Jitter, 8-Output PCIe Gen1 to Gen5 Clock Buffer PDF | HTML 16 Jul 2021

Design & development

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Evaluation board

CDCDB800EVM — CDCDB800 evaluation module is an 8-output LP-HCSL clock buffer for PCIe® Gen 1 to Gen 5 application

CDCDB800 evaluation module is an 8-output LP-HCSL, DB800ZL compliant, clock buffer capable of distributing the reference clock for PCIe® Gen 1 to Gen 5 application, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus interface and eight outputs enable pins to allow the (...)
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Application software & framework

TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
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Simulation model

CDCDB800 IBIS model

SNAM247.ZIP (30 KB) - IBIS Model
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFN (RSL) 48 View options

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