SNAU323 August   2025 LMK3H2104

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1Configuration Overview
    1. 1.1 LMK3H2104 Configuration Information
  4. 2Device Register Map
  5. 3Device Registers
  6. 4Revision History

1.1 LMK3H2104 Configuration Information

Table 1-1 Frequency Configuration
OTP Page OUT0 (MHz) OUT1 (MHz) OUT2 (MHz) OUT3 (MHz) REF0 (MHz) REF1 (MHz)
OTP Page 0 100 100 100 100 25 25
OTP Page 1 100 100 100 100 25 25
OTP Page 2 100 100 100 100 25 25
OTP Page 3 100 100 100 100 25 25
Table 1-2 I2C Configuration
OTP Page I2C Configuration
OTP Page 0

I2C Address: 0x68

1 Byte Register Addressing
OTP Page 1

I2C Address: 0x68

1 Byte Register Addressing
OTP Page 2

I2C Address: 0x68

1 Byte Register Addressing
OTP Page 3

I2C Address: 0x68

1 Byte Register Addressing

OTP Page 0

Table 1-3 GPI Settings, OTP Page 0
GPI Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPI0 Group OE, OE_GROUP_0 Inverted Enabled Disabled
GPI1 Group OE, OE_GROUP_1 Inverted Enabled Disabled
GPI2 Group OE, OE_GROUP_2 Inverted Enabled Disabled
Table 1-4 GPIO Settings, OTP Page 0
GPIO Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPIO0 Group OE, OE_GROUP_3 Inverted Enabled Disabled
GPIO1 Status Output, CLK_READY Normal Enabled Disabled
Table 1-5 Input Settings, OTP Page 0
Input Powered Up/Down Input Format Input Termination
IN_0 Powered Down N/A (IN0 Unused) None, DC
Table 1-6 Output Settings, OTP Page 0
Output Frequency (MHz) Format Clock Source Output State OE Group SSC Behavior
OUT0 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_0 Disabled
OUT1 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_1 Disabled
OUT2 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_2 Disabled
OUT3 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_3 Disabled
REF0 25 N/A PATH1 Disabled No OE Group Disabled
REF1 25 N/A PATH1 Disabled No OE Group Disabled

OTP Page 1

Table 1-7 GPI Settings, OTP Page 1
GPI Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPI0 Group OE, OE_GROUP_0 Inverted Enabled Disabled
GPI1 Group OE, OE_GROUP_1 Inverted Enabled Disabled
GPI2 Group OE, OE_GROUP_2 Inverted Enabled Disabled
Table 1-8 GPIO Settings, OTP Page 1
GPIO Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPIO0 Group OE, OE_GROUP_3 Inverted Enabled Disabled
GPIO1 Status Output, CLK_READY Normal Enabled Disabled
Table 1-9 Input Settings, OTP Page 1
Input Powered Up/Down Input Format Input Termination
IN_0 Powered Down N/A (IN0 Unused) None, DC
Table 1-10 Output Settings, OTP Page 1
Output Frequency (MHz) Format Clock Source Output State OE Group SSC Behavior
OUT0 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_0 Enabled, -0.1% Down-spread
OUT1 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_1 Enabled, -0.1% Down-spread
OUT2 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_2 Enabled, -0.1% Down-spread
OUT3 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_3 Enabled, -0.1% Down-spread
REF0 25 N/A PATH1 Disabled No OE Group Enabled, -0.1% Down-spread
REF1 25 N/A PATH1 Disabled No OE Group Enabled, -0.1% Down-spread

OTP Page 2

Table 1-11 GPI Settings, OTP Page 2
GPI Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPI0 Group OE, OE_GROUP_0 Inverted Enabled Disabled
GPI1 Group OE, OE_GROUP_1 Inverted Enabled Disabled
GPI2 Group OE, OE_GROUP_2 Inverted Enabled Disabled
Table 1-12 GPIO Settings, OTP Page 2
GPIO Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPIO0 Group OE, OE_GROUP_3 Inverted Enabled Disabled
GPIO1 Status Output, CLK_READY Normal Enabled Disabled
Table 1-13 Input Settings, OTP Page 2
Input Powered Up/Down Input Format Input Termination
IN_0 Powered Down N/A (IN0 Unused) None, DC
Table 1-14 Output Settings, OTP Page 2
Output Frequency (MHz) Format Clock Source Output State OE Group SSC Behavior
OUT0 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_0 Enabled, -0.3% Down-spread
OUT1 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_1 Enabled, -0.3% Down-spread
OUT2 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_2 Enabled, -0.3% Down-spread
OUT3 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_3 Enabled, -0.3% Down-spread
REF0 25 N/A PATH1 Disabled No OE Group Enabled, -0.3% Down-spread
REF1 25 N/A PATH1 Disabled No OE Group Enabled, -0.3% Down-spread

OTP Page 3

Table 1-15 GPI Settings, OTP Page 3
GPI Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPI0 Group OE, OE_GROUP_0 Inverted Enabled Disabled
GPI1 Group OE, OE_GROUP_1 Inverted Enabled Disabled
GPI2 Group OE, OE_GROUP_2 Inverted Enabled Disabled
Table 1-16 GPIO Settings, OTP Page 3
GPIO Pin Pin Behavior Polarity Internal Pull-Down Internal Pull-Up
GPIO0 Group OE, OE_GROUP_3 Inverted Enabled Disabled
GPIO1 Status Output, CLK_READY Normal Enabled Disabled
Table 1-17 Input Settings, OTP Page 3
Input Powered Up/Down Input Format Input Termination
IN_0 Powered Down N/A (IN0 Unused) None, DC
Table 1-18 Output Settings, OTP Page 3
Output Frequency (MHz) Format Clock Source Output State OE Group SSC Behavior
OUT0 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_0 Enabled, -0.5% Down-spread
OUT1 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_1 Enabled, -0.5% Down-spread
OUT2 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_2 Enabled, -0.5% Down-spread
OUT3 100 100 Ω LP-HCSL PATH1 Enabled OE_GROUP_3 Enabled, -0.5% Down-spread
REF0 25 N/A PATH1 Disabled No OE Group Enabled, -0.5% Down-spread
REF1 25 N/A PATH1 Disabled No OE Group Enabled, -0.5% Down-spread