SNLS440 Data sheet

SNLS440C MARCH 2013 – July 2016 DS90UH928Q-Q1

PRODUCTION DATA.

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾ ⁽³⁾

	MIN	MAX	UNIT
Supply Voltage – V_DD33 ⁽²⁾	−0.3	4	V
Supply Voltage – V_DDIO ⁽²⁾	−0.3	4	V
LVCMOS I/O Voltage	−0.3	(V_DDIO + 0.3)	V
Deserializer Input Voltage	−0.3	2.75	V
Junction Temperature		150	°C
Storage temperature, T_stg	−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The DS90UH928Q-Q1V_DD33 and V_DDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less than 1.5 ms with a monotonic rise.

(3) For soldering specifications, see product folder at www.ti.com and SNOA549.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002, all pins⁽¹⁾		±8000	V
		Charged device model (CDM), per AEC Q100-011, all pins		±1250	V
		Machine model (MM)		±250	V
		(IEC, powered-up only) R_D = 330 Ω, C_S = 150 pF	Air Discharge (Pins 40, 41, 44, and 45)	±15000	V
		(IEC, powered-up only) R_D = 330 Ω, C_S = 150 pF	Contact Discharge (Pins 40, 41, 44, and 45)	±8000	V
		(ISO10605) R_D = 330 Ω, C_S = 150 pF	Air Discharge (Pins 40, 41, 44, and 45)	±15000	V
		(ISO10605) R_D = 330 Ω, C_S = 150 pF	Contact Discharge (Pins 40, 41, 44, and 45)	±8000	V
		(ISO10605) R_D = 2 kΩ, C_S = 150 pF or 330 pF	Air Discharge (Pins 40, 41, 44, and 45)	±15000	V
		(ISO10605) R_D = 2 kΩ, C_S = 150 pF or 330 pF	Contact Discharge (Pins 40, 41, 44, and 45)	±8000	V

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
Supply Voltage (V_DD33)⁽¹⁾		3	3.3	3.6	V
LVCMOS Supply Voltage (V_DDIO)⁽¹⁾ ⁽²⁾	Connect V_DDIO to 3.3 V and use 3.3 V IOs	3	3.3	3.6	V
LVCMOS Supply Voltage (V_DDIO)⁽¹⁾ ⁽²⁾	Connect V_DDIO to 1.8 V and use 1.8 V IOs	1.71	1.8	1.89	V
Operating Free Air Temperature (T_A)		−40	25	105	°C
PCLK Frequency (out of TxCLKOUT±)		5		85	MHz
Supply Noise⁽³⁾				100	mV_P-P

(1) The DS90UH928Q-Q1V_DD33 and V_DDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less than 1.5 ms with a monotonic rise.

(2) V_DDIO should not exceed V_DD33 by more than 300 mV (V_DDIO < V_DD33 + 0.3 V).

(3) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the V_DD33 and V_DDIO supplies with amplitude >100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no error when the noise frequency is less than 50 MHz.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DS90UH928Q-Q1	UNIT
		RHS (WQFN)
		48 PINS
R_θJA	Junction-to-ambient thermal resistance	26.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	4.4	°C/W
R_θJB	Junction-to-board thermal resistance	4.3	°C/W
ψ_JT	Junction-to-top characterization parameter	0.1	°C/W
ψ_JB	Junction-to-board characterization parameter	4.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.8	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. ⁽¹⁾ ⁽²⁾ ⁽³⁾

PARAMETER		TEST CONDITIONS	PIN/FREQ.	MIN	TYP	MAX	UNIT
3.3 V LVCMOS I/O
V_IH	High Level Input Voltage	V_DDIO = 3.0 V to 3.6 V	GPIO[3:0], REG_GPIO[8:5], LFMODE, MAPSEL, BISTEN, BISTC, INTB_IN, OEN, OSS_SEL	2.0		V_DDIO	V
V_IL	Low Level Input Voltage	V_DDIO = 3.0 V to 3.6 V		GND		0.8	V
I_IN	Input Current	V_IN = 0 V or V_IN = 3.0 V to 3.6 V		−10	±1	+10	μA
V_IH	High Level Input Voltage	⁽⁴⁾	PDB	2.0		V_DDIO	V
V_IL	Low Level Input Voltage	⁽⁴⁾		GND		0.7	V
I_IN	Input Current	V_IN = 0 V or V_IN = 3.0 V to 3.6 V ⁽⁴⁾		−10	±1	+10	μA
V_OH	HIGH Level Output Voltage	I_OH = -4 mA	GPIO[3:0], REG_GPIO[8:5], MCLK, I2S_WC, I2S_CLK, I2S_D[A:D], LOCK, PASS	2.4		V_DDIO	V
V_OL	LOW Level Output Voltage	I_OL = +4 mA		0		0.4	V
I_OS	Output Short Circuit Current	V_OUT = 0 V⁽⁵⁾			−55		mA
I_OZ	Tri-state Output Current	V_OUT = 0 V or V_DDIO, PDB = L		−20		+20	μA
1.8 V LVCMOS I/O
V_IH	High Level Input Voltage	V_DDIO = 1.71 V to 1.89 V	GPIO[3:0], REG_GPIO[8:5], LFMODE, MAPSEL, BISTEN, BISTC, INTB_IN, OEN, OSS_SEL	0.65 * V_DDIO		V_DDIO	V
V_IL	Low Level Input Voltage	V_DDIO = 1.71 V to 1.89 V		0		0.35 * V_DDIO	V
I_IN	Input Current	V_IN = 0 V or V_IN = 1.71 V to 1.89 V		-10		10	μA
V_OH	HIGH Level Output Voltage	I_OH = -4 mA	GPIO[3:0], REG_GPIO[8:5], MCLK, I2S_WC, I2S_CLK, I2S_D[A:D], LOCK, PASS	V_DDIO - 0.45		V_DDIO	V
V_OL	LOW Level Output Voltage	I_OL = +4 mA		0		0.45	V
I_OS	Output Short Circuit Current	V_OUT = 0 V⁽⁵⁾			-35		mA
I_OZ	TRI-STATE® Output Current	V_OUT = 0 V or V_DDIO, PDB = L,		-20		20	μA
FPD-LINK (OpenLDI) LVDS OUTPUT
V_OD	Output Voltage Swing (single-ended)	Register 0x4B[1:0] = b'00 R_L = 100 Ω	TxCLK±, TxOUT[3:0]±	140	200	300	mV
V_OD	Output Voltage Swing (single-ended)	Register 0x4B[1:0] = b'01 R_L = 100 Ω		220	300	380	mV
V_ODp-p	Differential Output Voltage	Register 0x4B[1:0] = b'00 R_L = 100 Ω			400		mV
V_ODp-p	Differential Output Voltage	Register 0x4B[1:0] = b'01 R_L = 100 Ω			600		mV
ΔV_OD	Output Voltage Unbalance	R_L = 100 Ω			1	50	mV
V_OS	Common Mode Voltage			1.125	1.25	1.375	V
ΔV_OS	Offset Voltage Unbalance				1	50	mV
I_OS	Output Short Circuit Current	V_OUT = GND			-5		mA
I_OZ	Output TRI-STATE® Current	OEN = GND, V_OUT = V_DDIO or GND, 0.8 V≤V_IN≤1.6 V		-500		500	μA
FPD-LINK III RECEIVER
V_TH	Input Threshold High	V_CM = 2.1 V (Internal V_BIAS)	RIN±			50	mV
V_TL	Input Threshold Low			-50			mV
V_ID	Input Differential Threshold					100	mV
V_CM	Common-mode Voltage				2.1		V
R_T	Internal Termination Resistance (Differential)			80	100	120	Ω
SUPPLY CURRENT
I_DD1	Supply Current R_L = 100 Ω, PCLK = 85 MHz	Checkerboard Pattern	V_DD33= 3.6 V		190	250	mA
I_DDIO1			V_DDIO = 3.6 V		0.1	1	mA
I_DDIO1			V_DDIO = 1.89 V		0.1	1	mA
I_DD2		Random Pattern	V_DD33= 3.6 V		185		mA
I_DDIO2			V_DDIO = 3.6 V		0.1		mA
I_DDIO2			V_DDIO = 1.89 V		0.1		mA
I_DDZ	Supply Current — Power Down	PDB = 0 V, All other LVCMOS inputs = 0 V	V_DD33 = 3.6 V		3	8	mA
I_DDIOZ			V_DDIO = 3.6 V		100	500	μA
I_DDIOZ			V_DDIO = 1.89 V		50	250	μA

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.

(2) Typical values represent most likely parametric norms at V_DD33 = 3.3 V, V_DDIO = 1.8 V or 3.3 V, T_A= 25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except V_OD and ΔV_OD, which are differential voltages.

(4) PDB is specified to 3.3 V LVCMOS only and must be driven or pulled up to V_DD33 or to V_DDIO ≥ 3.0 V.

(5) I_OS is not specified for an indefinite period of time. Do not hold in short circuit for more than 500 ms or part damage may result.

6.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. ⁽¹⁾ ⁽²⁾ ⁽³⁾

PARAMETER		TEST CONDITIONS	PIN/FREQ.	MIN	TYP	MAX	UNIT
GPIO
t_GPIO,FC	GPIO Pulse Width, Forward Channel	See ⁽⁴⁾	GPIO[3:0], PCLK = 5 MHz to 85 MHz	2/PCLK			s
t_GPIO,BC	GPIO Pulse Width, Back Channel	See ⁽⁴⁾	GPIO[3:0]	20			µs
RESET
t_LRST	PDB Reset Low Pulse	See ⁽⁴⁾	PDB	2			ms
LOOP-THROUGH MONITOR OUTPUT
E_W	Differential Output Eye Opening Width	R_L = 100 Ω, Jitter freq > f/40	CMLOUTP, CMLPUTN		0.4		UI
E_H	Differential Output Eye Height	R_L = 100 Ω, Jitter freq > f/40	CMLOUTP, CMLPUTN		300		mV
FPD-LINK LVDS OUTPUT
t_TLHT	Low to High Transition Time	R_L = 100 Ω	TxCLK±, TxOUT[3:0]±		0.25	0.5	ns
t_THLT	High to Low Transition Time	R_L = 100 Ω	TxCLK±, TxOUT[3:0]±		0.25	0.5	ns
t_DCCJ	Cycle-to-Cycle Output Jitter	PCLK = 5 MHz	TxCLK±		170	275	ps
t_DCCJ	Cycle-to-Cycle Output Jitter	PCLK = 85 MHz	TxCLK±		35	55	ps
t_TTPn	Transmitter Pulse Position	5 MHz ≤ PCLK ≤ 85 MHz n = [6:0] for bits [6:0] See Figure 13	TxOUT[3:0]±		0.5 + n		UI
Δt_TTP	Offset Transmitter Pulse Position (bit 6 - bit 0)	PCLK = 85 MHz			0.1		UI
t_DD	Delay Latency				147*T		T
t_TPDD	Power Down Delay Active to OFF				900		µs
t_TXZR	Enable Delay OFF to Active				6		ns
FPD-LINK III INPUT
IJT	Input Jitter⁽⁶⁾	PCLK = 5 MHz to 85 MHz Sinusoidal Jitter Frequency > PCLK / 15	RIN±			0.35	UI
t_DDLT	Lock Time⁽⁴⁾	5 MHz ≤ PCLK ≤ 85 MHz	RIN±, LOCK		6	40	ms
LVCMOS OUTPUTS
t_CLH	Low-to-High Transition Time	C_L = 8 pF	LOCK, PASS		3	7	ns
t_CHL	High-to-Low Transition Time	C_L = 8 pF	LOCK, PASS		2	5	ns
BIST MODE
t_PASS	BIST PASS Valid Time		PASS		800		ns
I2S TRANSMITTER
t_J	Clock Output Jitter		MCLK		2		ns
T_I2S	I2S Clock Period Figure 10, ⁽⁴⁾ ⁽⁵⁾	PCLK=5 MHz to 85 MHz	I2S_CLK, PCLK = 5 MHz to 85 MHz		2/PCLK or >77		ns
T_HC	I2S Clock High Time Figure 10, ⁽⁵⁾		I2S_CLK	0.35			T_I2S
T_LC	I2S Clock Low Time Figure 10, ⁽⁵⁾		I2S_CLK	0.35			T_I2S
t_{SR_I2S}	I2S Set-up Time Figure 10, ⁽⁵⁾		I2S_WC I2S_D[A:D]	0.2			T_I2S
t_{HR_I2S}	I2S Hold Time Figure 10, ⁽⁵⁾		I2S_WC I2S_D[A:D]	0.2			T_I2S

(2) Typical values represent most likely parametric norms at V_DD33 = 3.3 V, V_DDIO = 1.8 V or 3.3 V, T_A = 25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except V_OD and ΔV_OD, which are differential voltages.

(4) Specification is ensured by design and is not tested in production.

(5) I2S specifications for t_LC and t_HC pulses must each be greater than 1 PCLK period to ensure sampling and supersedes the 0.35*T_{I2S_CLK} requirement. t_LC and t_HC must be longer than the greater of either 0.35*T_{I2S_CLK} or 2*PCLK.

(6) UI – Unit Interval is equivalent to one serialized data bit width 1UI = 1 / (35 × PCLK). The UI scales with PCLK frequency.

6.7 Timing Requirements for the Serial Control Bus

Over 3.3-V supply and temperature ranges unless otherwise specified. ⁽¹⁾ ⁽²⁾

			MIN	MAX	UNIT
f_SCL	SCL Clock Frequency	Standard Mode	0	100	kHz
f_SCL	SCL Clock Frequency	Fast Mode	0	400	kHz
t_LOW	SCL Low Period	Standard Mode	4.7		µs
t_LOW	SCL Low Period	Fast Mode	1.3		µs
t_HIGH	SCL High Period	Standard Mode	4.0		µs
t_HIGH	SCL High Period	Fast Mode	0.6		µs
t_HD;STA	Hold time for a start or a repeated start condition ⁽³⁾	Standard Mode	4.0		µs
t_HD;STA	Hold time for a start or a repeated start condition ⁽³⁾	Fast Mode	0.6		µs
t_SU:STA	Set Up time for a start or a repeated start condition ⁽³⁾	Standard Mode	4.7		µs
t_SU:STA	Set Up time for a start or a repeated start condition ⁽³⁾	Fast Mode	0.6		µs
t_HD;DAT	Data Hold Time ⁽³⁾	Standard Mode	0	3.45	µs
t_HD;DAT	Data Hold Time ⁽³⁾	Fast Mode	0	0.9	µs
t_SU;DAT	Data Set Up Time ⁽³⁾	Standard Mode	250		ns
t_SU;DAT	Data Set Up Time ⁽³⁾	Fast Mode	100		ns
t_SU;STO	Set Up Time for STOP Condition ⁽³⁾	Standard Mode	4		µs
t_SU;STO	Set Up Time for STOP Condition ⁽³⁾	Fast Mode	0.6		µs
t_BUF	Bus Free Time Between STOP and START ⁽³⁾	Standard Mode	4.7		µs
t_BUF	Bus Free Time Between STOP and START ⁽³⁾	Fast Mode	1.3		µs
t_r	SCL & SDA Rise Time, ⁽³⁾	Standard Mode		1000	ns
t_r	SCL & SDA Rise Time, ⁽³⁾	Fast Mode		300	ns
t_f	SCL & SDA Fall Time, ⁽³⁾	Standard Mode		300	ns
t_f	SCL & SDA Fall Time, ⁽³⁾	Fast mode		300	ns

(2) Typical values represent most likely parametric norms at V_DD33 = 3.3 V, V_DDIO = 1.8 V or 3.3 V, T_A = +25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured.

(3) Specification is ensured by design and is not tested in production.

6.8 Timing Requirements

			NOM	UNIT
t_R	SDA RiseTime – READ	SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 16	430	ns
t_F	SDA Fall Time – READ	SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 16	20	ns
t_SU;DAT	Set Up Time – READ	Figure 16	560	ns
t_HD;DAT	Hold Up Time – READ	Figure 16	615	ns

6.9 DC and AC Serial Control Bus Characteristics

Over 3.3 V supply and temperature ranges unless otherwise specified. ⁽¹⁾ ⁽²⁾ ⁽³⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IH	Input High Level	SDA and SCL	0.7* V_DDIO		V_DD33	V
V_IL	Input Low Level Voltage	SDA and SCL	GND		0.3* V_DD33	V
V_HY	Input Hysteresis			50		mV
V_OL		SDA or SCL, I_OL = 1.25 mA	0		0.36	V
I_in		SDA or SCL, V_IN = V_DDIO or GND	-10		10	µA
t_SP	Input Filter			50		ns
C_in	Input Capacitance	SDA or SCL		5		pF

(1) The Electrical Characteristics tables list specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except V_OD and ΔV_OD, which are differential voltages.