SNLS604F September   2020  – April 2025 DP83TG720S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
    2. 4.1 Pin States
    3. 4.2 Pin Power Domain
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 LED Drive Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Diagnostic Tool Kit
        1. 6.3.1.1 Signal Quality Indicator
        2. 6.3.1.2 Time Domain Reflectometry
        3. 6.3.1.3 Built-In Self-Test For Datapath
          1. 6.3.1.3.1 Loopback Modes
          2. 6.3.1.3.2 Data Generator
          3. 6.3.1.3.3 Programming Datapath BIST
        4. 6.3.1.4 Temperature and Voltage Sensing
        5. 6.3.1.5 Electrostatic Discharge Sensing
      2. 6.3.2 Compliance Test Modes
        1. 6.3.2.1 Test Mode 1
        2. 6.3.2.2 Test Mode 2
        3. 6.3.2.3 Test Mode 4
        4. 6.3.2.4 Test Mode 5
        5. 6.3.2.5 Test Mode 6
        6. 6.3.2.6 Test Mode 7
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Down
      2. 6.4.2 Reset
      3. 6.4.3 Standby
      4. 6.4.4 Normal
      5. 6.4.5 Sleep
      6. 6.4.6 State Transitions
        1. 6.4.6.1 State Transition #1 - Standby to Normal
        2. 6.4.6.2 State Transition #2 - Normal to Standby
        3. 6.4.6.3 State Transition #3 - Normal to Sleep
        4. 6.4.6.4 State Transition #4 - Sleep to Normal
      7. 6.4.7 Media Dependent Interface
        1. 6.4.7.1 MDI Master and MDI Slave Configuration
        2. 6.4.7.2 Auto-Polarity Detection and Correction
      8. 6.4.8 MAC Interfaces
        1. 6.4.8.1 Reduced Gigabit Media Independent Interface
        2. 6.4.8.2 Serial Gigabit Media Independent Interface
      9. 6.4.9 Serial Management Interface
        1. 6.4.9.1 Direct Register Access
        2. 6.4.9.2 Extended Register Space Access
          1. 6.4.9.2.1 Write Operation (No Post Increment)
          2. 6.4.9.2.2 Read Operation (No Post Increment)
          3. 6.4.9.2.3 Write Operation (Post Increment)
          4. 6.4.9.2.4 Read Operation (Post Increment)
    5. 6.5 Programming
      1. 6.5.1 Strap Configuration
      2. 6.5.2 LED Configuration
      3. 6.5.3 PHY Address Configuration
    6. 6.6 Register Maps
      1. 6.6.1 Register Access Summary
      2. 6.6.2 DP83TG720 Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
    3. 7.3 Power Supply Recommendations
    4. 7.4 Compatibility with TI's 100BT1 PHY
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Signal Traces
        2. 7.5.1.2 Return Path
        3. 7.5.1.3 Physical Medium Attachment
        4. 7.5.1.4 Metal Pour
        5. 7.5.1.5 PCB Layer Stacking
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
      1. 10.1.1 Packaging Information
      2. 10.1.2 Tape and Reel Information

6.4.9.1 Direct Register Access

Direct register access can be used for the first 31 registers (0x0h through 0x1Fh).