SNLS604G September   2020  – June 2026 DP83TG720S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin States
    2. 4.2 Pin Power Domain
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 LED Drive Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Diagnostic Tool Kit
        1. 6.3.1.1 Signal Quality Indicator
        2. 6.3.1.2 Time Domain Reflectometry
        3. 6.3.1.3 Built-In Self-Test For Datapath
          1. 6.3.1.3.1 Loopback Modes
          2. 6.3.1.3.2 Data Generator
          3. 6.3.1.3.3 Programming Datapath BIST
        4. 6.3.1.4 Temperature and Voltage Sensing
        5. 6.3.1.5 Electrostatic Discharge Sensing
      2. 6.3.2 Compliance Test Modes
        1. 6.3.2.1 Test Mode 1
        2. 6.3.2.2 Test Mode 2
        3. 6.3.2.3 Test Mode 4
        4. 6.3.2.4 Test Mode 5
        5. 6.3.2.5 Test Mode 6
        6. 6.3.2.6 Test Mode 7
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Down
      2. 6.4.2 Reset
      3. 6.4.3 Standby
      4. 6.4.4 Normal
      5. 6.4.5 Sleep
      6. 6.4.6 State Transitions
        1. 6.4.6.1 State Transition #1 - Standby to Normal
        2. 6.4.6.2 State Transition #2 - Normal to Standby
        3. 6.4.6.3 State Transition #3 - Normal to Sleep
        4. 6.4.6.4 State Transition #4 - Sleep to Normal
      7. 6.4.7 Media Dependent Interface
        1. 6.4.7.1 MDI Master and MDI Slave Configuration
        2. 6.4.7.2 Auto-Polarity Detection and Correction
      8. 6.4.8 MAC Interfaces
        1. 6.4.8.1 Reduced Gigabit Media Independent Interface
        2. 6.4.8.2 Serial Gigabit Media Independent Interface
      9. 6.4.9 Serial Management Interface
        1. 6.4.9.1 Direct Register Access
        2. 6.4.9.2 Extended Register Space Access
          1. 6.4.9.2.1 Write Operation (No Post Increment)
          2. 6.4.9.2.2 Read Operation (No Post Increment)
          3. 6.4.9.2.3 Write Operation (Post Increment)
          4. 6.4.9.2.4 Read Operation (Post Increment)
    5. 6.5 Programming
      1. 6.5.1 Strap Configuration
      2. 6.5.2 LED Configuration
      3. 6.5.3 PHY Address Configuration
  8. 7 Register Maps
    1. 7.1 Register Access Summary
    2. 7.2 DP83TG720 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
    3. 8.3 Power Supply Recommendations
    4. 8.4 Compatibility with TI's 100BT1 PHY
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Signal Traces
        2. 8.5.1.2 Return Path
        3. 8.5.1.3 Physical Medium Attachment
        4. 8.5.1.4 Metal Pour
        5. 8.5.1.5 PCB Layer Stacking
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.4.6.3 State Transition #3 - Normal to Sleep

Sleep state can be entered either locally or by remote link-partner.

Local sleep entry for Master mode phy :

  • Step 1 : Write bit[7] = 'b1 of register[0x018B].
  • Step 2 : Write reg0x042F = 0x0007, reg0x041E = 0x0100
  • Step 3: Make "wake" pin low and hold it low for sleep mode.

Local sleep entry for Slave mode phy :

  • Step 1 : Write bit[8] = 'b0 of register[0x018B] register.
  • Step 2 : Write bit[7] = 'b1 of register[0x018B] register.
  • Step 3 : Write reg0x042F = 0x0007, reg0x041E = 0x0100
  • Step 4: Make "wake" pin low and hold it low for sleep mode.

Remote sleep entry for Master mode phy :

  • Master can be put to sleep remotely by slave PHY provided the below instructions when the device is already linked-up with the link partner.
  • Step 1: Write bit[8] = 'b1 of register [0x018B] register and bit[7] = 'b1 of register[0x018B] register.
  • Step 2: Make "wake" pin low
  • Step 3: Phy will go into sleep mode with loss of energy on Line

Remote sleep entry for Slave mode phy :

  • Step 1 : Write bit[7] = 'b1 of register[0x018B] register.
  • Step 2 : Make "wake" pin low.
  • Step 3: Phy will go into sleep mode with loss of energy on line (when master will go quite : no data, no send-s).This can be achieved by putting link-partner in managed mode (where device is not allowed to start link-up sequence).

Note: Phy will go into sleep mode only if power supplies are disconnected using INH signal as shown in figure Required Implementation for Sleep Mode.