SNLS604G September   2020  – June 2026 DP83TG720S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin States
    2. 4.2 Pin Power Domain
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 LED Drive Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Diagnostic Tool Kit
        1. 6.3.1.1 Signal Quality Indicator
        2. 6.3.1.2 Time Domain Reflectometry
        3. 6.3.1.3 Built-In Self-Test For Datapath
          1. 6.3.1.3.1 Loopback Modes
          2. 6.3.1.3.2 Data Generator
          3. 6.3.1.3.3 Programming Datapath BIST
        4. 6.3.1.4 Temperature and Voltage Sensing
        5. 6.3.1.5 Electrostatic Discharge Sensing
      2. 6.3.2 Compliance Test Modes
        1. 6.3.2.1 Test Mode 1
        2. 6.3.2.2 Test Mode 2
        3. 6.3.2.3 Test Mode 4
        4. 6.3.2.4 Test Mode 5
        5. 6.3.2.5 Test Mode 6
        6. 6.3.2.6 Test Mode 7
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Down
      2. 6.4.2 Reset
      3. 6.4.3 Standby
      4. 6.4.4 Normal
      5. 6.4.5 Sleep
      6. 6.4.6 State Transitions
        1. 6.4.6.1 State Transition #1 - Standby to Normal
        2. 6.4.6.2 State Transition #2 - Normal to Standby
        3. 6.4.6.3 State Transition #3 - Normal to Sleep
        4. 6.4.6.4 State Transition #4 - Sleep to Normal
      7. 6.4.7 Media Dependent Interface
        1. 6.4.7.1 MDI Master and MDI Slave Configuration
        2. 6.4.7.2 Auto-Polarity Detection and Correction
      8. 6.4.8 MAC Interfaces
        1. 6.4.8.1 Reduced Gigabit Media Independent Interface
        2. 6.4.8.2 Serial Gigabit Media Independent Interface
      9. 6.4.9 Serial Management Interface
        1. 6.4.9.1 Direct Register Access
        2. 6.4.9.2 Extended Register Space Access
          1. 6.4.9.2.1 Write Operation (No Post Increment)
          2. 6.4.9.2.2 Read Operation (No Post Increment)
          3. 6.4.9.2.3 Write Operation (Post Increment)
          4. 6.4.9.2.4 Read Operation (Post Increment)
    5. 6.5 Programming
      1. 6.5.1 Strap Configuration
      2. 6.5.2 LED Configuration
      3. 6.5.3 PHY Address Configuration
  8. 7 Register Maps
    1. 7.1 Register Access Summary
    2. 7.2 DP83TG720 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
    3. 8.3 Power Supply Recommendations
    4. 8.4 Compatibility with TI's 100BT1 PHY
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Signal Traces
        2. 8.5.1.2 Return Path
        3. 8.5.1.3 Physical Medium Attachment
        4. 8.5.1.4 Metal Pour
        5. 8.5.1.5 PCB Layer Stacking
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5.1 Strap Configuration

The DP83TG720S-Q1 uses functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up and hardware reset (through either the RESET_N pin or register access). The strap pins support 2-levels and 3-levels, which are described in greater detail below. Configuration of the device is done through strapping or through serial management interface.

Note:

  • Strap pins are functional pins after reset is deasserted and must not be connected directly to VCC or GND.
  • Pull up strap resistors are sufficient to enter different strap modes.
  • Pull down strap resistor can have application for LED pin straps. Refer to LED Configuration section.

DP83TG720S-Q1 Strap Circuit Figure 6-18 Strap Circuit

Table 6-16 Recommended 3-level Strap Resistor Ratios
MODE Recommended RH (kΩ)1
for VDDIO = 3.3V		 Recommended RH (kΩ)2
for VDDIO = 2.5V		 Recommended RH (kΩ)1
for VDDIO = 1.8V
1 OPEN OPEN OPEN
2 13 12 4
3 4.5 2 0.8
  1. 10% resistor accuracy
  2. 1% resistor accuracy
Table 6-17 Recommended 2-level Strap Resistor
MODE Recommended RH (kΩ)12
1 OPEN
2 2.49
  1. 10% resistor accuracy
  2. To gain more margin in customer application for 1.8V VDDIO, either 2.1K±10% pull-up can be used or resistor accuracy of 2.49K resistor can be limited to 1%.

The following table describes the DP83TG720S-Q1 configuration bootstraps:

Table 6-18 2-level Bootstraps
PIN NAME PIN NO. STRAP MODE STRAP FUNCTION DESCRIPTION
RX_D0 26 1 (default) MAC[0] = 0 MAC Interface Selection [0]. Refer to Table 6-19 for full description.
2 MAC[0] = 1
RX_D1 25 1 (default) MAC[1] = 0 MAC Interface Selection [1]. Refer to Table 6-19 for full description.
2 MAC[1] = 1
RX_D2 24 1 (default) MAC[2] = 0 MAC Interface Selection [2]. Refer to Table 6-19 for full description.
2 MAC[2] = 1
LED_0

35

 1 (default) MS = 0 MDI Master Slave Select.
MS = 0 Slave
MS = 1 Master
2 MS = 1
LED_1 6 1 (default) AUTO = 0 Autonomous Disable
AUTO = 0 Autonomous
AUTO = 1 Managed
2 AUTO = 1
Table 6-19 MAC Interface Selection Bootstraps
MAC[2] MAC[1] MAC[0] DESCRIPTION
0 0 0

SGMII (4-wire)
0 0 1 RESERVED
0 1 0 RESERVED
0 1 1 RESERVED
1 0 0 RGMII (Align Mode)
1 0 1 RGMII (TX Shift Mode)
1 1 0 RGMII (TX and RX Shift Mode)
1 1 1 RGMII (RX Shift Mode)
Table 6-20 3-Level Bootstrap: PHY Address
PHY_AD[3:0] RX_CTRL
STRAP MODE		 STRP_1
STRAP MODE		 DESCRIPTION
0000 1 1 PHY Address: 0x0000 (0)
0001 - - RESERVED
0010 - - RESERVED
0011 - - RESERVED
0100 2 1 PHY Address: 0x0004 (4)
0101 3 1 PHY Address: 0x0005 (5)
0110 - - RESERVED
0111 - - RESERVED
1000 1 2 PHY Address: 0x0008 (8)
1001 - - RESERVED
1010 1 3 PHY Address: 0x000A (10)
1011 - - RESERVED
1100 2 2 PHY Address: 0x000C (12)
1101 3 2 PHY Address: 0x000D (13)
1110 2 3 PHY Address: 0x000E (14)
1111 3 3 PHY Address: 0x000F (15)