SNLS766A July   2024  – April 2026 TDP20MB421

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High-Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 5-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Flat Gain
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 DP 2.1 and HDMI 2.1 Mainlink Signal Conditioning
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TDP20MB421 RUA Package, 42-Pin WQFN (Top View)Figure 4-1 RUA Package, 42-Pin WQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
MODE 41 I, 5-level Sets device control configuration modes. The 5-level IO pin is defined in Table 6-1. The pin is used at device power up or in normal operation mode.
L0: Pin Mode – device control configuration is done solely by strap pins.
L1 or L2: SMBus/I2C Mode – device control configuration is done by an external controller with SMBus/I2C primary. This pin along with ADDR pin set the secondary address of the device.
L3 and L4 (Float): RESERVED – TI internal test modes.
EQ0 /ADDR 40 I, 5-level In Pin Mode:
The EQ0 and EQ1 pins sets receiver linear equalization CTLE (AC gain) for all channels according to Table 6-2. These pins are sampled at device power up only.
In SMBus/I2C Mode:
The ADDR pin in conjunction with the MODE pin sets SMBus / I2C secondary address according to Table 6-4. The pin is sampled at device power-up only.
EQ1 20 I, 5-level
GAIN /SDA 1 I, 5-level / IO In Pin Mode:
Flat gain (broadband gain – DC and AC) from the input to the output of the device for all channels. The device also provides AC (high frequency) gain in the form of equalization controlled by EQ pins or SMBus/I2C registers. The pin is sampled at device power up only.
In SMBus/I2C Mode:
3.3V SMBus/I2C data. External pullup resistor such as 4.7kΩ required for operation.
GND EP, 2, 6, 9, 12, 16, 21, 30, 39 P Ground reference for the device.
EP: the Exposed Pad at the bottom of the QFN package. The EP is used as the GND return for the device. Connect the EP to one or more ground planes through the low resistance path. A via array provides a low impedance path to GND. The EP also improves thermal dissipation.
PD 18 I, 3.3V LVCMOS 2-level logic controlling the operating state of the redriver. Active in both Pin Mode and SMBus/I2C Mode. The pin has a weak 1MkΩ internal pulldown resistor.
High: power down for all channels
Low: power up, normal operation for all channels
TEST /SCL 42 I, 5-level / IO In Pin Mode:
TI Test mode. Use external 1kΩ pulldown resistor instead.
In SMBus/I2C Mode:
3.3V SMBus/I2C clock. External pullup resistor such as 4.7kΩ required for operation.
RXA3P 37 I Inverting differential RX input – Port A, Channel 3.
RXA3N 38 I Noninverting differential RX input – Port A, Channel 3.
RXA2P 33 I Inverting differential RX input – Port A, Channel 2.
RXA2N 34 I Noninverting differential RX input – Port A, Channel 2.
RXA1P 28 I Inverting differential RX input – Port A, Channel 1.
RXA1N 29 I Noninverting differential RX input – Port A, Channel 1.
RXA0P 24 I Inverting differential RX input – Port A, Channel 0.
RXA0N 25 I Noninverting differential RX input – Port A, Channel 0.
RXB3P 35 I Inverting differential RX input – Port B, Channel 3.
RXB3N 36 I Noninverting differential RX input – Port B, Channel 3.
RXB2P 31 I Inverting differential RX input – Port B, Channel 2.
RXB2N 32 I Noninverting differential RX input – Port B, Channel 2.
RXB1P 26 I Inverting differential RX input – Port B, Channel 1.
RXB1N 27 I Noninverting differential RX input – Port B, Channel 1.
RXB0P 22 I Inverting differential RX input – Port B, Channel 0.
RXB0N 23 I Noninverting differential RX input – Port B, Channel 0.
SEL 17 I, 3.3V LVCMOS Selects the mux path. Active in both Pin Mode and SMBus/I2C Mode. The pin has a weak internal pulldown resistor. Exercise the SEL pin in system implementations for mux selection between Port A vs Port B.
L: Port A selected.
H: Port B selected.
TX3P 4 O Inverting differential TX output, Channel 3.
TX3N 3 O Noninverting differential TX output, Channel 3.
TX2P 8 O Inverting differential TX output, Channel 2.
TX2N 7 O Noninverting differential TX output, Channel 2.
TX1P 11 O Inverting differential TX output, Channel 1.
TX1N 10 O Noninverting differential TX output, Channel 1.
TX0P 15 O Inverting differential TX output, Channel 0.
TX0N 14 O Noninverting differential TX output, Channel 0.
RSVD3 19 O TI internal test pin. Keep no connect.
VCC 5, 13 P Power supply, VCC = 3.3V ± 10%. Connect the VCC pins on this device through a low-resistance path to the board VCC plane.
(1) I = input, O = output, P = power, GND = ground