SNLU278 March   2021 DS160PR412 , DS160PR421

 

  1. 1Access Methods
    1. 1.1 Register Programming Through I2C orSMBus
  2. 2Register Map Overview
  3. 3Example Programming Sequences
    1. 3.1 Set CTLE Gain Level
    2. 3.2 Reset RX Detect State Machine
    3. 3.3 Set SEL Input
    4. 3.4 Set CTLE DC Gain Level
    5. 3.5 Set VOD Level
  4. 4SHARE Registers
  5. 5CHANNEL Registers
  6. 6References

3.1 Set CTLE Gain Level

The DS160PR4xx requires manual CTLE tuning. The CTLE gain level can be changed by modifying the value of each CTLE stage (EQ1 and EQ0) . The CTLE level may be set individually for each channel or broadcast to all channels. Table 3-1 shows an example sequence for setting the CTLE gain level to 5.0 dB at 8 GHz (CTLE Index 2) on the Bank 0 channels and to 7.0 dB (CTLE Index 4) on the Bank 1 channels using individual writes to each channel. Use register values provided in Table 3-3 to set the CTLE gain level to any other available value.

Table 3-1 Sequence to Set CTLE Level on Each Channel Individually
Step Register Set Operation Register Address
[HEX]		 Register Value
[HEX]		 Write Mask
[HEX]		 Comment
1 Bank 0: Channel 0 Write 0x01 0x08 0x3F Set CTLE to Index 2 on Channel 0.
2 Bank 0: Channel 1 Write 0x21 0x08 0x3F Set CTLE to Index 2 on Channel 1.
3 Bank 1: Channel 2 Write 0x01 0x08 0x3F Set CTLE to Index 2 on Channel 2.
4 Bank 1: Channel 3 Write 0x21 0x08 0x3F Set CTLE to Index 2 on Channel 3.

Assuming 0x18 and 0x19 are the I2C/SMBus addresses for the Channel Banks 0 and 1 respectively, the following is the XML batch script of the sequence in Table 3-1:

<i2c_write addr="0x18" count="0" radix"16">01 08</i2c_write>
<i2c_write addr="0x18" count="0" radix"16">21 08</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">01 11</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">21 11</i2c_write>

Table 3-2 shows an example sequence to set the CTLE gain level to 5.0 dB at 8 GHz (CTLE Index 2) on Bank 0 channels and to 7.0 dB (CTLE Index 4) on Bank 1 channels using a broadcast write to each channel bank.

Table 3-2 Sequence to Broadcast CTLE Level to All Channels
Step Register Set Operation Register Address
[HEX]		 Register Value
[HEX]		 Write Mask
[HEX]		 Comment
1 Bank 0: Channels 0-1 Write 0x81 0x08 0x3F Set EQ to Index 2 on Channels 0-1.
2 Bank 1: Channels 2-3 Write 0x81 0x11 0x3F Set EQ to Index 4 on Channels 2-3.

Assuming 0x18 and 0x19 are the I2C/SMBus addresses for the Channel Banks 0 and 1 respectively, the following is the XML batch script of the sequence in Table 3-2:

<i2c_write addr="0x18" count="0" radix"16">81 08</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">81 11</i2c_write>

Table 3-3 gives a CTLE Control Register value as a function of CTLE Index (0 - 15). Example CTLE Control Register addresses are given in Table 3-1 and Table 3-2.

Table 3-3 CTLE Control Register Value as a Function of CTLE Index
CTLE Index CTLE Gain at 4 GHz (dB) CTLE Gain at 8 GHz (dB) CTLE Control Register Value
[HEX]
0 -0.25 -0.5 0x40
1 2.0 4.0 0x43
2 2.5 5.0 0x08
3 3.0 6.0 0x0A
4 4.0 7.0 0x11
5 4.5 7.5 0x12
6 5.0 8.0 0x13
7 6.0 9.5 0x1A
8 7.0 10.0 0x1B
9 8.0 11.0 0x23
10 8.5 12.5 0x2B
11 9.0 13.0 0x2C
12 9.5 14.5 0x2D
13 10.0 15.0 0x35
14 10.5 16.0 0x36
15 12.0 18.0 0x3F